University of Florida EEL 3701—Fall 2001 Drs. Schwartz & Gugel
Department of Electrical & Computer Engineering Professors in ECE
Page 1/2 Revision 2 24-Oct-01—5:53 PM
LAB 7: Elementary Central Processing Unit (CPU) Design
OBJECTIVES
The objective of this lab is to design a controller for the
ALU designed in Lab 5. A 2-bit instruction field will be used
to control a simple state machine that in turn will be used to
set the MUX lines in the ALU according to what type of
instruction is designated for execution.
MATERIALS
Prototype Board, Wires, Switches, LEDs and 7032 Board
INTRODUCTION - LAB 5 ALU MUX SIGNALs
The ALU designed in Lab 5 consisted of (4) 4:1 MUXs on
the inputs of REGA and (4) 4:1 MUXs on the inputs of
REGB. The select lines for these MUXs were designated
MSA1:0 and MSB1:0, respectively. For a quick review,
the MUXs selected a bus in the following manner:
The outputs of REGA and REGB were then passed to a
combinatorial logic block and the results of this were then
passed to (4) 8:1 MUXs. The select lines for these (4)
MUXs were designated as MSC2:0. For review purposes,
these (3) lines selected the following functions:
INTRODUCTION – NEW ALU CONTROLLER
A state machine controller and Instruction Register (IR) are
now added to the ALU to facilitate the execution of simple
instructions. See Figure 1 for the total system components.
The IR register contains 2 bits which represent the
following four instructions:
The ASM Diagram for the Controller is shown in Figure 2.
All instructions execute in one cycle (plus one cycle to load
the IR register). except for the load immediate data (IR = 01).
This instruction takes two cycles.
Instruction Register Design
The IR is clocked like a typical bank of D Flip-Flops,
however, it has a new feature; it can be loaded or not loaded
depending on “IR.LD”. When IR.LD is true, data is loaded
into the register and when IR.LD is false, new data is not
loaded into the register (hold condition). This register can
be simply realized with a 2:1 MUX on the input of each flip-
flops of the IR. When the 2:1 MUX select line is low, select
the IR outputs back to the IR inputs and when the select line
is high, run the INPUT bus signals to the inputs of the IR.
PRE-LAB REQUIREMENTS
1. Complete the ASM diagram shown in Figure 2; i.e.,
put in the actual MUX select signals in the ASM
diagram.
2. Create a Next State table, K-Maps and logic
equations for the ALU Controller.
3. Using the graphic editor design in MaxPlusII, add
the IR and Controller circuitry to your Lab 5 ALU.
4. Simulate and test all instructions created in the
Controller circuitry.
IN-LAB REQUIREMENTS
1. Download your design to the 7032 breakout board.
2. Connect LEDs and switches to the breakout board;
verify it functions as specified in the Pre-Lab
Requirements.
3. You will need a debounced switch for the CLK input.
QUESTION
1. Why did we require the new Instruction Register in this
design?
2. In this lab you are setting the INPUT bus by hand. If
you wanted to read or fetch this value from memory,
what could you add to do this automatically for you
every CLK cycle?
3. How would you add more instructions (i.e. 8 instead of
4) to the controller?
HELPFUL HINTS
Debug as you design for a much better chance of success.
When something goes wrong, i.e., when a design does not
work as expected, what should you do? Don’t panic! Think
of some experiments that you can do to break the problem
down into pieces in order to isolate the error. A useful tool
for debugging a design is to add outputs for some of the
internal signals, i.e., signals that are neither outputs nor
inputs of your design. This will allow you to “peer inside” a
design both in simulation and with the actual hardware.
MSA1/
MSB1 MSA0/
MSB0 Bus Selected as Input
to REGA/REGB
0 0 INPUT Bus
0 1 REGA Output Bus
1 0 REGB Output Bus
1 1 OUTPUT Bus
MSC2:0 Action
000 REGA Bus to OUTPUT Bus
001 REGB Bus to OUTPUT Bus
010 complement of REGA Bus to OUTPUT Bus
011 bit wise AND REGA/REGB Bus to OUTPUT Bus
100 bit wise OR REGA/REGB Bus to OUTPUT Bus
101 sum of REGA Bus & REGB Bus to OUTPUT Bus
110 shift REGA Bus left one bit to OUTPUT Bus
111 shift REGA Bus right one bit to OUTPUT Bus
00 Move REGA contents => REGB
01 Load REGA with data on the INPUT bus
10 Sum REGA & REGB and place contents => REGA
11 Left Shift REGA 1 bit => REGA
