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ARM instruction set
ARM versions.
ARM assembly language.
ARM programming model.
ARM memory organization.
ARM data operations.
ARM flow of control.
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Embedded Systems Programming, ARM instruction set 20, Study notes of Embedded Systems Programming
Slides on: ARM versions. ARM assembly language. ARM programming model. ARM memory organization. ARM data operations. ARM flow of control
Typology: Study notes
2010/2011
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ARM instruction set
(^) ARM versions. (^) ARM assembly language. (^) ARM programming model. (^) ARM memory organization. (^) ARM data operations. (^) ARM flow of control.
ARM versions
(^) ARM architecture has been extended over several versions. (^) We will concentrate on ARM7.
ARM programming model
r r r r r r r r r r r r r r r r15 (PC) CPSR 31 0 N Z C V
Endianness
(^) Relationship between bit and byte/word ordering defines endianness: byte 3 byte 2 byte 1 byte 0 byte 0 byte 1 byte 2 byte 3 bit 31 (^) bit 0 bit 0 bit 31 little-endian big-endian
ARM status bits
(^) Every arithmetic, logical, or shifting operation sets CPSR bits: (^) N (negative), Z (zero), C (carry), V (overflow). (^) Examples: (^) -1 + 1 = 0: NZCV = 0110. (^231) -1+1 = -2^31 : NZCV = 1001.
ARM data instructions
(^) Basic format: ADD r0,r1,r (^) Computes r1+r2, stores in r0. (^) Immediate operand: ADD r0,r1,# (^) Computes r1+2, stores in r0.
Data operation varieties
(^) Logical shift: (^) fills with zeroes. (^) Arithmetic shift: (^) fills with ones. (^) RRX performs 33-bit rotate, including C bit from CPSR above sign bit.
ARM comparison instructions
(^) CMP : compare (^) CMN : negated compare (^) TST : bit-wise AND (^) TEQ : bit-wise XOR (^) These instructions set only the NZCV bits of CPSR.
ARM load/store instructions
(^) LDR, LDRH, LDRB : load (half-word, byte) (^) STR, STRH, STRB : store (half-word, byte) (^) Addressing modes: (^) register indirect : LDR r0,[r1] (^) with second register : LDR r0,[r1,-r2] (^) with constant : LDR r0,[r1,#4]
ARM ADR pseudo-op
(^) Cannot refer to an address directly in an instruction. (^) Generate value by performing arithmetic on PC. (^) ADR pseudo-op generates instruction required to calculate address: ADR r1,FOO
C assignment, cont’d.
SUB r3,r3,r2 ; complete computation of x ADR r4,x ; get address for x STR r3,[r4] ; store value of x
Example: C assignment
C:
y = a*(b+c); (^) Assembler: ADR r4,b ; get address for b LDR r0,[r4] ; get value of b ADR r4,c ; get address for c LDR r1,[r4] ; get value of c ADD r2,r0,r1 ; compute partial result ADR r4,a ; get address for a LDR r0,[r4] ; get value of a
Example: C assignment
C:
z = (a << 2) | (b & 15); (^) Assembler: ADR r4,a ; get address for a LDR r0,[r4] ; get value of a MOV r0,r0,LSL 2 ; perform shift ADR r4,b ; get address for b LDR r1,[r4] ; get value of b AND r1,r1,#15 ; perform AND ORR r1,r0,r1 ; perform OR
C assignment, cont’d.
ADR r4,z ; get address for z STR r1,[r4] ; store value for z