Embedded Systems Programming, Multiprocessors (22), Study notes of Embedded Systems Programming

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Overview

 Why multiprocessors?

 The structure of multiprocessors.

 Elements of multiprocessors:

 (^) Processing elements.  (^) Memory.  (^) Interconnect.

Why multiprocessing?

 True parallelism:

 (^) Task level.  (^) Data level.

 May be necessary to meet real-time

requirements.

Heterogeneous multiprocessors

 Will often have a heterogeneous

structure.

 (^) Different types of PEs.  (^) Specialized memory structure.  (^) Specialized interconnect.

Multiprocessor system-on-chip

 Multiple processors.

 (^) CPUs, DSPs, etc.  (^) Hardwired blocks.  (^) Mixed-signal.

 Custom memory system.

 Lots of software.

Terminology

 PE: processing element.

 Interconnection network: may

require more than one clock cycle to

transfer data.

 Message: address+data packet.

Generic multiprocessor

 (^) Shared memory:  (^) Message passing: PE mem PE mem PE mem … … Interconnect network PE mem PE mem PE mem … Interconnect network

Shared memory implementation

 Memory blocks are in address space.

 Memory interface sends messages

through network to addressed

memory block.

Message passing

implementation

 Program provides processor address,

data/parameters.

 (^) Usually through API.

 Packet(s) interface appears as I/O device.

 (^) Packet routed through network to interface.

 Recipient must decode parameters to

determine how to handle the message.

Matching PEs to tasks

 Factors:

 (^) Word size.  (^) Operand types.  (^) Performance.  (^) Energy/power consumption.

 Hardwired function units:

 (^) Performance.  (^) Interface.

Task allocation

 Tasks may be created at:

 (^) Design time (video encoder).  (^) Run time (user interface).

 Tasks may be assigned to processing

elements at:

 (^) Design time (predictable load).  (^) Run time (varying load).

Parallel memory systems

 True

concurrency---

several memory

blocks can

operate

simultaneously.

PE mem PE mem PE mem … … Interconnect network

Cache consistency

 Problem:

caches hide

memory

updates.

 Solution: have

caches snoop

changes.

PE mem PE cache cache network mem

Network topologies

 Major choices.

 (^) Bus.  (^) Crossbar.  (^) Buffered crossbar.  (^) Mesh.  (^) Application-specific.

Bus network

 Advantages:

 (^) Well-understood.  (^) Easy to program.  (^) Many standards.

 Disadvantages:

 (^) Contention.  (^) Significant capacitive load.