ECE 4110 - Sequential Logic Design
Exam 2 - Fall 2006
NOTES: Closed book, except one sheet of handwritten notes and the VHDL Quick
Reference Card are allowed. Show ALL your work for full credit. Please draw and write
NEATLY (If I cannot read it, I must mark it WRONG). Do all work in pencil and put all
answers on your engineering paper, with one problem per page. Clearly label all answers
with the problem number. Follow all the specified class formats, including VHDL.
1. [25 pts] Discuss the topic of testing a combinational circuit with simulation by
answering these questions. What are the names of the two major types of simulation?
What are the advantages and uses of each type? How do you test a small circuit (<5
inputs)? What is different about testing a larger circuit? How do you test the larger
circuit?
2. [25 pts] Analyze the following VHDL code and draw the logic diagram directly
implied by the VHDL code in terms of gates and standard MSI functions, without any
simplification. Assume all the appropriate libraries and packages have been included.
ENTITY thisone IS
PORT ( a, b, s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
c, d : IN STD_LOGIC ;
f : OUT STD_LOGIC ;
g : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ) ;
END thisone;
ARCHITECTURE behav OF thisone IS
BEGIN
PROCESS (s, a, b)
BEGIN
CASE s IS
WHEN "00" | "10" =>
f <= '1'; g <= a AND b ;
WHEN "01" =>
f <= c; g <= NOT a(0) & a(1) ;
WHEN OTHERS =>
f <= '0'; g <= "11" ;
END CASE ;
IF b(0) = '1' THEN f <= c OR d; ELSE f <= 'Z'; END IF;
END PROCESS ;
END behav ;
