ECE 4110 - Sequential Logic Design
Final Exam - Fall 2005
NOTES: Closed book, except three sheets of handwritten notes and the VHDL Quick
Reference Card are allowed. Do not make any marks on the supplied handout sheets.
Read the problems CAREFULLY! Show ALL your work for full credit. Please draw and
write NEATLY (If I cannot read it, I must mark it WRONG). Do all work in pencil and
put all answers on your engineering paper. Start each problem's work on a new page.
Follow the specified class formats. Clearly label all work with the problem number and
part letter.
1. [20 pts] Give short answers regarding programmable logic devices:
a. Explain why some projects might not fit into an Altera EPM7128S CPLD, even
though they used less than the maximum of 128 macrocells and they used less
than the maximum of 100 input/output pins. See the Max 7000S block diagram
handout.
b. Precisely what type of logic device (NOT transistor) is programmed with the
user’s logic function within a basic PAL-type programmable device (e.g.
PAL16L8)?
c. Precisely what type of logic device is programmed with the user’s logic function
within the CLB of a Xilinx XC4000-series FPGA?
d. Explain why each of the three inputs to the M1 mux could be useful in certain
applications of the XC9500. See the XC9500 block diagram handout.
2. [20 pts] A state machine is represented by the following state/output table, which was
derived from a word description. Perform the step-by-step manual FSM design process
for a minimal cost solution, stopping with the final minimal SOP equations (NO logic
diagram). Clearly label each step in the process. Use the simplest state assignment
(A,B,C = 00,01,10 respectively), with the state bits ordered Q1 Q0, MSB to LSB, using
D flip-flops.
| N |
S | 0 1 | Y
------------------
A | A C | 0
B | C B | 1
C | B A | 1
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S*
