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Introduction to
CMOS VLSI
Design
Lecture 1C: Circuits
Peter KoggeJoseph Nahas University of Notre Dame
Fall 2009
Slightly modified and rearranged from original 2008 slides by Jay Brockman
Based on lecture slides by David Harris, Harvey Mudd College
http://www.cmosvlsi.com/coursematerials.html
CMOS VLSI Design
1C: Circuits
Outline: Circuits C
CMOS Tristates CMOS Multiplexers CMOS Latches & Flip-Flops
CMOS VLSI Design
1C: Circuits
Slide 3
Tristates
Tristate buffer
produces Z when not enabled
EN
A^
Y
0
0
0
1
1
0
1
1
A^
Y EN A^
Y EN EN
CMOS VLSI Design
1C: Circuits
Tristates
Tristate buffer
produces Z when not enabled
EN
A^
Y
0
0
Z
0
1
Z
1
0
0
1
1
1
A^
Y EN A^
Y EN EN
CMOS VLSI Design
1C: Circuits
Slide 5
Nonrestoring Tristate
Transmission gate acts as tristate buffer
- Only two transistors– But
nonrestoring
- Noise on A is passed on to Y
A
Y
EN EN
CMOS VLSI Design
1C: Circuits
Tristate Inverter
Tristate inverter produces restored output
- Violates conduction complement rule– Because we want a Z outputA
Y
EN EN
Vdd
CMOS VLSI Design
1C: Circuits
Slide 7
Tristate Inverter
Tristate inverter produces restored output
- Violates conduction complement rule– Because we want a Z outputA
Y
EN
A
Y EN = 0Y = 'Z'
Y EN = 1Y = A A
EN
Vdd
Vdd
Vdd
CMOS VLSI Design
1C: Circuits
Multiplexers
multiplexer
chooses between two inputs
S^
D
D
Y
0
X^
0
0
X^
1
1
0
X
1
1
X
S (^01)
D0 D
Y
CMOS VLSI Design
1C: Circuits
Slide 13
Transmission Gate Mux ^
Nonrestoring mux uses two transmission gates– Only 4 transistors
S S
D0 D
Y
S
CMOS VLSI Design
1C: Circuits
Slide 14
Inverting Mux
Inverting multiplexer
- Use compound AOI22– Or pair of tristate inverters– Essentially the same thing Noninverting multiplexer adds an inverter
D0^ S
D
Y
S D0 D
Y (^01)
S
Y
D
D1 S
S S
S
S
S
Vdd
Vdd
Vdd
CMOS VLSI Design
1C: Circuits
Slide 15
4:1 Multiplexer
4:1 mux chooses one of 4 inputs using two selects
CMOS VLSI Design
1C: Circuits
Slide 16
4:1 Multiplexer
4:1 mux chooses one of 4 inputs using two selects
- Two levels of 2:1 muxes– Or four tristates
S D0 D
(^0101)
0 1
Y S
D2D
D0 D1 D2 D
Y
S1S0 S1S0 S1S0 S1S
CMOS VLSI Design
1C: Circuits
Slide 17
D Latch
When CLK = 1, latch is
transparent
- D flows through to Q like a buffer When CLK = 0, the latch is
opaque
- Q holds its old value independent of D a.k.a.
transparent latch
or
level-sensitive latch
CLK
D^
Q
Latch
CLK D Q
CMOS VLSI Design
1C: Circuits
Slide 18
D Latch Design
Multiplexer chooses D or old Q
(^10)
D
CLK
Q^
CLK
CLK CLK
CLK
D
Q^
Q Q
CMOS VLSI Design
1C: Circuits
Slide 19
D Latch Operation
D^ CLK = 1
Q Q
D^ CLK = 0
Q Q
CLK D Q
CMOS VLSI Design
1C: Circuits
Slide 20
D Flip-flop
When CLK rises, D is copied to Q At all other times, Q holds its value a.k.a.
positive edge-triggered flip-flop
,^ master-slave
flip-flop
Flop CLK D^
Q
CLK D Q
