Explicit Moment Matching - Circuit Simulation - Lecture Slides, Slides of Computer Science

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CSE245: Computer-Aided Circuit

Simulation and Verification

Lecture Note 4

Model Order Reduction (2)

Model Order Reduction: Overview

2

• Explicit Moment Matching
  • AWE, Pade Approximation
• Implicit Moment Matching (Projection Framework)
  • Krylov Subspace Methods
    • PRIMA, SPRIM
• Gaussian Elimination
  • TICER, Y-Delta Transformation

Parasitic Extraction

4

R,L,C Extraction

Model Order Reduction

Moment Matching Projection method

• Key ideal of Model Order reduction:

“Moments Matching” and “Projection”

• Step1: identify internal state function and variables.
• Step2: Compose moments matching. (Pade, Taylor expression).
• Step3: Project matrix with matching moments. (Block Arnoldi (PRIMA) or block Lanczos (PVL))
• Step4: Get the reduced state function.

Congruence Transformation

7

• Definition:
  • Property: Congruence transformation preserves semidefiniteness of the matrix

Krylov Subspace

8

• Given an n x n matrix A and a n x 1 vector r the Krylov subspace is defined as
• Given an n x q matrix Vq whose column vectors are v 1 , v 2 , …, vq. The span of Vq is defined as

PRIMA

10

• step 1. Circuit Formulation
  • step 2. Find the projection matrix Vq
    • Arnoldi Process to generate Vq

PRIMA: Properties

11

• Preserves passivity, and hence stability
• Matches moments up to order q (proof in next slide)
• Original matrices A and C are structured.
• But and do not preserve this structure in general

SPRIM

13

• Suppose Vq is generated by Arnoldi process as in PRIMA. Partition Vq accordingly
• Recall
• Construct New Projection Matrix

SPRIM

14

• Congruence Transformation
• Now structure is preserved
  • Transfer function for the reduced order model

TICER ( TI me C onstant E quilibration R eduction)

16

• 1. Calculate time constant for each node
• 2. Eliminate quick nodes and slow nodes
• Quick node: Eliminate if
• Slow node: Eliminate if
• 3. Insert new R’s/C’s between former neighbors of N
• If nodes j and k had been connected to N through g (^) jN and g (^) kN , add a conductance of value gjN g (^) kN /G (^) N between j and k
• If nodes j and k had been connected to N through c (^) jN and g (^) kN , add a capacitor of value cjN g (^) kN /G (^) N between j and k

TICER: Issues

17

• Fill-in
  • The order that nodes are eliminated matters
    • Minimum Degree Ordering can be implemented to reduce fill-in
  • May need to limit number of incident resistors to control fill-in
• Error control leads to low reduction ratio
• Accuracy
  • Matches 0th^ moment at every node in the reduced circuit.
  • Only Correct DC op point guaranteed