Comparison of Intel 82573L Ethernet NIC and Token Ring: Exploring Network Interfaces, Slides of Computer Applications

An introduction to programming the intel 82573l gigabit ethernet network interface controller (nic). It covers the history of token ring and ethernet technologies, their differences, and the features of the intel 82573l nic. The document also includes instructions on accessing the nic's registers and some troubleshooting tips.

Typology: Slides

2012/2013

Uploaded on 04/17/2013

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Exploring a modern NIC
An introduction to programming
the Intel 82573L gigabit ethernet
network interface controller
Docsity.com
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Exploring a modern NIC

An introduction to programming

the Intel 82573L gigabit ethernet

network interface controller

Token Ring

host-1 host-2 host-3 host-

Token Ring Media Access Unit

Technology developed by IBM in the 1960s

Ethernet LAN

host-1 host-2 host-

host-

HUB “Collision Domain”

CSMA/CD = “Carrier Sense Multiple Access/Collision Detection”

Ethernet Versus Token Ring

ETHERNET

Ethernet is the most widely used data sending protocol. Each computer listens to the cable before sending data over the network. If the network is clear, the computer will transmit. If another PC is already transmitting data, the computer will wait and try again when the line is clear. If two computers transmit at the same time a collision occurs. Each computer then waits a random amount of time before attempting to retransmit. The delay caused by collisions and retransmitting is minimal and does not normally affect the speed of transmission on the network.

TOKEN RING

The Token Ring protocol was developed by IBM but it has become obsolete in the face of ethernet technology. The computers are connected so that data travels around the network from one computer to another in a logical ring. If a computer does not have information to transmit, it simply passes the a token on to the next workstation. If a computer wishes to transmit and receives an empty token, it attaches data to the token. The token then proceeds around the ring until it comes to the computer for which the data is meant.

Posted by Heather C Moll (Last Updated March 24 2004)

Our ‘anchor’ cluster

D-Link 24-port 10/100/1000-Mbps Ethernet Switched Hub

computer science department’s Local Area Network

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anchor

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anchor

anchor

anchor

anchor

anchor

Acronyms

• PCI = Peripheral Component Interconnect

• MAC = Media Access Controller

• Phy = Physical-layer functions

• AMT = Active Management Technology

• LOM = LAN On Motherboard

• BOM = Bill Of Materials

External Architecture

PCI/PCI-e Bus

10/100/1000 PHY

MAC/Controller

MDI interface

SM Bus interface EEPROM

Flash interface

LED indicators

S/W Defined pins

GMII/MII

MDIO interface interface

Access to PRO/1000 registers

• Device registers are hardware mapped to

a range of addresses in physical memory

• You obtain the location (and the length) of

this memory-range from a BAR register in

the nic device’s PCI Configuration Space

• Then you request the Linux kernel to setup

an I/O ‘remapping’ of this memory-range

to ‘virtual’ addresses within kernel-space

portability syntax

• Linux provides device-driver writers with

some macros for accessing i/o-memory:

#include <asm/io.h>

unsigned int datum;

iowrite32( datum, address );

datum = ioread32( address );

module_init()

#include <linux/pci.h> #include <asm/io.h> #define E1000_STATUS 0x unsigned int iomem_base, iomem_size; void *io;

// remap the device’s i/o-memory into kernel space devp = pci_get_device( VENDOR_ID, DEVICE_ID, NULL ); if ( !devp ) return –ENODEV; iomem_base = pci_resource_start( devp, 0 ); iomem_size = pci_resource_len( devp, 0 ); io = ioremap_nocache( iomem_base, iomem_size ); if ( !io ) return –ENOSPC;

// read and display the nic’s STATUS register device_status = ioread32( io + E1000_STATUS ); printk( “ Device Status Register = 0x%08X \n”, status );

Confusion in vendor’s manual?

• The manual shows Device Status as a

‘read-only’ register, but later on it states

that bit #10 “is cleared by writing 0b to it.”

• Bit #31 in Device Status register is marked

‘reserved’ in the Developer’s Manual (with

initial value shown as ‘0’), but we observe

it’s value being ‘1’ on ‘anchor’ machines

• Do these represent errata? omissions?

Quotation

Many companies do an excellent job of providing information to help customers use their products... but in the end there's no substitute for real-life experiments: putting together the hardware, writing the program code, and watching what happens when the code executes. Then when the result isn't as expected -- as it often isn't -- it means trying something else or searching the documentation for clues.

-- Jan Axelson, author, Lakeview Research (1998)

In-class exercise

• Experiment with writing all 0’s into the nic’s

Device Status register, and see if values of

any bits actually get changed; then also try

writing all 1’s into this register, in order to

discover which bits indeed are “ read-only ”

• You can use our ‘gbstatus.c’ module as a

starting-point for these experimentations