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4 problems, 6 pages Exam Two Solutions 13 March 2003
Problem 1 (6 parts, 40 points) Numbers and Arithmetic
Part A (4 points) Convert these octal values into decimal notation:
octal notation decimal notation 73 7(8)+3 = 59
25.3 2(8)+5+(3/8) = 21.
Part B (4 points) Convert these hexadecimal values into octal notation:
hexadecimal notation octal notation 0xABC 1010 1011 11002 = 5274 8
0x3FD.E4 001111111101.111001002 = 1775.71 (^8)
Part C (10 points) For each problem below, (a) compute the addition using the rules of arithmetic, (b) indicate whether an error occurs assuming all numbers are expressed using a six bit two’s complement representation, and (c) indicate whether an error occurs assuming all numbers are expressed using a six bit unsigned representation.
0 1 0 1 0 1
result
signed
error? Yes^ No
unsigned
error? No^ Yes
Part D (12 points) Convert each subtraction problem (X-Y=Z) below to an addition problem (X+(-Y)=Z) and compute the result of the addition. Also indicate whether an error occurs assuming all numbers are expressed using a six bit two’s complement representation and then indicate whether an error occurs using a six bit unsigned representation.
1 0 1 1 0 -1 1 1 0 1
Result
Signed
Error? No^ Yes
Unsigned
Error? Yes^ No
4 problems, 6 pages Exam Two Solutions 13 March 2003
Part E (4 points) The adder below adds two four bit numbers A and B and produces a four bit result S. Add extra digital logic to support subtraction as well as addition. Label inputs X 3 , X 2 ,
X 1 , X 0 , Y 3 , Y 2 , Y 1 , Y 0 , ADD / SUB and outputs Z 3 , Z 2 , Z 1 , Z 0. For this part, do not implement overflow error detection.
A 3 A 2 A 1 A 0 B^3 B^2 B^1 B^0
S 3 S 2 S 1 S 0
Cin
X 3 X 2 X 1 X 0
Y 3 Y 2 Y 1 Y 0
Z 3 Z 2 Z 1 Z 0
ADD/SUB
Cout
Part F (6 points) Below is a partial implementation of an overflow error detector for the adder/subtractor in part E. It detects errors in addition or subtraction of signed and unsigned numbers. Complete the implementation by labeling the inputs using signals from part E (e.g.,
ADD / SUB and S 3 ) and the additional input signal Unsigned / Signed which is 1 if the numbers
being added/subtracted are two’s complement numbers and which is 0 if the numbers are unsigned. For maximum credit, label all inputs (marked with “?”). B^3 S^3
Cout ADD/SUB
A^3 A^3 B^3 S^3
1 0 2-to-1 MUX Sel
Unsigned/Signed
Error
(or C in)
4 problems, 6 pages Exam Two Solutions 13 March 2003
Problem 3 (2 parts, 15 points) Reengineering Counters
Part A (5 points) Suppose you have a counter with a count enable CE and an active high clear CLR. The counter has two outputs (O 1 and O 0 ) which form an unsigned integer (O 1 O 0 ). Its behavior is described by the following timing diagram. Each dotted vertical line denotes the end of one full clock cycle. What type of counter is this?
CE
CLR
Clock
Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14
This is a divide by 3 counter.
Part B (10 points) Suppose you are given the following incorrect implementation of a counter. Complete the timing diagram below by showing the outputs (O 0 and O 1 ) for clock cycles 7 through 14.
TE Out Clr
TE Out Clr
O 0
CLR O 1
CE
CE
CLR
Clock
Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14
4 problems, 6 pages Exam Two Solutions 13 March 2003
Problem 4 (2 parts, 25 points) Registers and Timing
Part A (10 points) Design an RS latch using NOR gates only. Label inputs R and S. Label output OUT. Do not attempt to employ mixed logic notation.
OUT
R
S
Show the behavior of this RS latch by completing the OUT column in the truth table below. In the Comment column, give a one-word description of each case (e.g., “Latch”).
R S OUT Comment 0 0 Q 0 Latch 0 1 1 Set 1 0 0 Reset 1 1 0 Invalid
Part B (15 points) Consider the register implemented below.
In Out
En
Latch
In Out
En
Latch
mux out
IN s
WE
OUT
A
Φ 1 Φ 2
Assume the following signals are applied to your register. Draw the signal at point A (output of the first latch) and the output signal Out. Assume A and Out start at zero.
Φ 1
Φ 2
In
WE
Out
A
