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ECE 2030 -- Introduction to Computer Engineering EXAM #1 SOLUTION February 7, 2001 Page 1 of 4
Problem 1. (12 points)
For each section of the following problem, given a function in one format express the same function in the other specified format(s). Note: “algebraic” refers to functions written in a format similar to the following: F = A B + C (D + E).
A. (4 points) Given F(A, B, C) = Σm (0, 1, 3, 4, 6) , express the function in algebraic sum-of- minterm and product-of-maxterm form.
F(A, B, C) = A B C + A B C + A B C + A B C + A B C (sum-of-minterm)
F(A, B, C) = (A + B + C) (A + B + C) (A + B + C) (product-of-maxterm)
B. (4 points) Given G(A, B, C) = A B + B(A + C) , complete the truth table and Karnaugh map below for this function.
A B C G 0 0 0 1 0 0 1 0 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 0 1 1 1 0
1 0
1 1
0 0
1 1
C AB 00
01
11 10
0 1
C. (4 points) Given the truth table below, complete the Karnaugh map and the short-hand SOP and POS expressions for this function.
0 1 0 1
0 1 1 0
A
BC
0
1
A B C W^00 01 11
W(A, B, C) = Σm ( 1, 2, 5, 7 )
W(A, B, C) = ΠM ( 0, 3, 4, 6 )
February 7, 2001 Page 2 of 5
Problem 2. (14 points)
A. (6 points) A CMOS switch network is shown below. Write the connectivity functions for
the pull-up and pull-down networks, FPU and FPD. Complete the truth table for this network, specifying the circuit output as “0,” “1,” “float,” or “short” for each input combination.
FPU = (A + C) B
FPD = A C + B C
A B C F
1 0 1 float 1 1 0 1 1 1 1 1
B. (8 points) Complete each of the switch-logic diagrams below by constructing the missing network as the dual of the pull-up or pull-down network given. Write the logic expression for the function implemented by each switch network.
G = (Y + Z) (X Z + Y) = Y Z + Y (X + Z) M = (R + T) (S + T) = R T + S T
S
M
R
T
T
R^ S
T^ T
A
F
C
C
B
A (^) B
C
Z
Z
Y
X Y
Z
G Y
Y X Z
February 7, 2001 Page 4 of 5
Problem 4. (14 points)
A. (8 points) Given the mixed-logic schematic below, write an algebraic expression for the function it implements. Your expression should correspond to the circuit structure given; do not attempt to minimize the expression. Then, determine the number of each type of physical logic gate that would be required to implement this circuit as drawn.
D E
C
B
A
F
F = ( A B ) ( B + B C ) ( D E )
# of gates: 1 AND _ 1 _ OR _ 2 _ NAND _ 1 _ NOR _ 5 _ INVERTER
B. (6 points) Given the function specified below, draw a mixed-logic schematic to implement it using only physical NOR gates and inverters. Your schematic should correspond to the expression given; do not attempt to minimize the expression. You should make a reasonable effort to minimize the number of inverters required. Then, determine the number of each type of physical logic gate that would be required to implement this circuit as drawn.
G = ( W + X ) X Y + ( X + Z )
Z
Y
X
W
G
# of gates: _ 5 __ NOR __ 5 _ INVERTER
