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Final Exam with Solutions | Solid State Devices | ECE 6163, Exams of Solid State Physics

University of Virginia (UVA)Solid State Physics
Prof. Lloyd Harriott

Material Type: Exam; Professor: Harriott; Class: Solid State Devices; Subject: Electrical and Computer Engineering; University: University of Virginia; Term: Spring 2008;

Typology: Exams

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Name:____Solutions_____________________________
ECE 663 Solid State Devices
Final Exam Spring 2008
Assigned 4/29/09 Due 5/6/08
This exam is a take-home exam and is due at my office (THN C219) by noon on 5/6/08.
No late papers will be accepted. Please read each question carefully and follow
directions.
You are only allowed to use your textbooks, class notes, homework assignments and
other materials on the class website. You are not allowed to work with anyone else or
use materials from previous years of this course or any websites other than the course
website.
Show all your work and/or Mathcad sheets, etc. in your answers.
Use this sheet as a cover sheet for your answers. Be sure to sign the pledge. I will put the
grade on the first page of the answers behind the cover sheet so that you will maintain
some privacy with your grade when you pick up your papers. I will send out e-mail when
the papers have been graded. The grades will be posted to the Toolkit gradebook. You
may pick up your papers in my office after they have been graded. The point values are
noted for each question totaling 100 points plus the five-point bonus question if you filled
out the end of semester course evaluation. This exam counts as 30% of your final grade
in the course.
On my honor as a student, I have neither given nor received unauthorized assistance on
this exam.
(sign name above)
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Download Final Exam with Solutions | Solid State Devices | ECE 6163 and more Exams Solid State Physics in PDF only on Docsity!

Name:____Solutions_____________________________

ECE 663 Solid State Devices

Final Exam Spring 2008

Assigned 4/29/09 Due 5/6/

This exam is a take-home exam and is due at my office (THN C219) by noon on 5/6/.

No late papers will be accepted. Please read each question carefully and follow

directions.

You are only allowed to use your textbooks, class notes, homework assignments and

other materials on the class website. You are not allowed to work with anyone else or

use materials from previous years of this course or any websites other than the course

website.

Show all your work and/or Mathcad sheets, etc. in your answers.

Use this sheet as a cover sheet for your answers. Be sure to sign the pledge. I will put the

grade on the first page of the answers behind the cover sheet so that you will maintain

some privacy with your grade when you pick up your papers. I will send out e-mail when

the papers have been graded. The grades will be posted to the Toolkit gradebook. You

may pick up your papers in my office after they have been graded. The point values are

noted for each question totaling 100 points plus the five-point bonus question if you filled

out the end of semester course evaluation. This exam counts as 30% of your final grade

in the course.

On my honor as a student, I have neither given nor received unauthorized assistance on

this exam.

(sign name above)

1. Imagine that you have just been hired by a company that wants to design and build a

Bluetooth gadget to connect your laptop to your printer. Your part of the project is to

design a transistor to be used in the RF amplifier output section. The company wants to

build a completely integrated product. That is, the analog, digital and memory circuits

are to be all on one chip. Given the digital and memory designs, you are stuck with a

Boron doped p-type Silicon substrate (N

A

15

/cm

3

). You can use B, P, or As

implantation to create doped regions. The silicon material has a minority carrier lifetime

of 10

sec and has electron and hole mobility given by:

  

x N

n 17

1 0. 698 10

1252

88

x N

p 17

Where N is the dopant concentration. The requirements are that the transistor be an npn

bipolar transistor with a common emitter current gain of 1000. Further, this will be a

battery-powered device and all voltages must be less than the battery voltage of 9 volts.

Supply a specification table for all of the parameters necessary for me to verify the

operation of your transistor. You need to include the dc biases with polarity. You should

include all relevant effects to generate an answer with accuracy in the 10% range. (

points)

I assumed that I could achieve reasonable p and n type dopings with ion implants and

thus the design is based on the emitter, collector, and base doping as well as the

metallurgical base width. It was necessary to calculate the effective base width in order

to get an accurate measure of the transistor performance. The portion of the emitter-

base and more importantly base-collector base depletion widths inside the base were

calculated and subtracted off. The bias voltages were somewhat arbitrary but chosen to

be within the capability of the battery. The MathCad document below shows the result of

some trial-and-error calculations aiming for a gain of 1000. I adjusted the base width to

get close to the desired gain value.

0

 14

farad

cm

V

biEB

k

T

q

 ln N E

N

B

n i

2

  V

biEB

 0.775volt EB built-in voltage

EB depletion width

W

EB

2 K

s

0

q

 V

biEB

V

BE

 

N

E

N

B

W

EB

 5

  cm

Part that is in the base

W

EBB

W

EB

N

E

N

E

N

B

W

EBB

 5

  cm

V

biCB

k

T

q

 ln N C

N

B

n i

2

  V

biCB

 0.656volt CB built-in voltage

CB depletion width

W

CB

2 K

s

0

q

 V

biCB

V

CB

 

N

C

N

B

W

CB

 4

  cm

Part that is in the base

W

CBB

W

CB

N

C

N

C

N

B

W

CBB

 5

  cm

diffusion Lengths

L

pC

D

pC

L

pE

D

pE

  L

nB

D

nB

L

pE

 3

  cm L nB

 3

  cm L pC

 3

  cm

L

B

L

nB

 L

C

L

pC

L

E

L

pE

n B

n i

2

N

B

 p C

n i

2

N

C

p E

n i

2

N

E

n B

4

 cm

 3

p C

5

 cm

 3

p E

100 cm

 3

need to find effective base width by subtracting out depletions from E-B and C-B junctions

find depletion width on the base side for the EB junction:

K

s

dc

3

dc

D

E

D

B

N

B

N

E

W

L

E

W

L

B

2

Common Emitter Gain

dc

Common Base Gain

dc

T

T

T

I

Cn

I

En

Base Transport

I

En

I

E

Emitter efficiency:

I

C

 4

  amp

I

C

I

Cn

I

Cp

I

Cn

 4

  amp

I

Cp

 15

  amp

I

Cn

q A

D

nB

W

 n B

 exp q

V

BE

k T

I

Cp

 qA

D

pC

L

pC

 p C

collector currents:

I

E

 4

I   amp E

I

En

I

Ep

I

Ep

 7

  amp

I

En

 4

  amp

I

En

q A

D

nB

W

 n B

 exp q

V

BE

k T

I  

Ep

q A

D

pE

L

pE

 p E

 exp q

V

BE

k T

Emitter currents:

we can neglect the terms with exponentials involving V CB

W 8.987 10

 7

  m

effective base width=W W W B

W

EBB

 W

CBB

The device in the sketch is an NPN bipolar transistor in active bias mode. From left to

right we have Emitter, Base, and Collector. The Emitter-Base junction looks forward

biased while the Base-Collector junction looks reverse biased. The equation in the upper

right describes the electron current injected into the base and collected in the collector

as being inversely proportional to the base width. This is meant to represent the base

transport factor with the narrow base approximation where the minority carrier current

in the base decreases linearly with base width. The equation in the lower part of the

board represents the hole current going from the base to the emitter as being inversely

proportional to the product minority carrier diffusion length, L

p

and the emitter doping

(we used N

D

for this instead of 

n

). This comes from the ideal diode (or Shockley)

equation and is the hole component of the saturation current. It gives the amount of

“backward” injection from Base to Emitter. Finally, I’m sure he would have noted that

the ratio of I

n

to I

p

in the sketch determined the gain of the transistor when used as an

amplifier (common emitter) as was the goal of inventing the transistor in the first place.

b) Show that for any narrow base BJT, if the emitter efficiency is close to unity, the

common-emitter current gain is approximately 

dc

=2L

B

2

/W

2

. (5 points)

3. The first transistor, demonstrated in 1947, is pictured below in the photograph and

accompanying diagram. Contrary to popular belief, this device was not a bipolar junction

transistor and in fact, contained no p-n junctions at all. The device was constructed from

a slab of n-type Germanium with an electrical contact on the back side. The front side of

the slab was contacted at two closely spaced points (about 50 microns apart) with gold

foil contacts (the gold foil was glued to the plastic wedge and then slit with a razor blade

to form two closely spaced contacts). One of the contacts had a negative voltage (about

10 volts) with respect to the slab back side contact and the other a (smaller) positive

voltage (about 1 volt). An AC signal was superimposed on the input circuit and current

(and power) gain was observed in the output circuit. Using what you have learned in this

course, explain how this device worked. You can use words and sketches, equations are

not necessary. (10 points)

T

T

T

T

T

dc

dc

dc

 

2

cosh /

B

Ep B

Cp

T

L

W

I W L

I

2

2

W

L

L

W

B

B

T

dc

The invention of the transistor shown above came about from studies conducted to

investigate the surface properties of semiconductors. John Bardeen had explained the

failure of earlier experiments aimed at getting field effect devices to work in terms of the

trapped surface charge (surface states). He and Walter Brattan were conducting

experiments to try to understand surface conduction in semiconductors when they

discovered that they could get current and voltage amplification with two closely spaced

contacts. In the device above, each of the gold metal contacts form what we now call

Schottky contacts(metal-semiconductor). They were observed to be rectifying rather than

ohmic. The contact with the large negative voltage is reverse biased and conducts only

leakage (reverse saturation) current under normal circumstances. The contact with the

positive voltage is forward biased and conducts current easily. When the two contacts

are in close proximity (minority carrier diffusion length), the injected carriers (holes)

n -type Germanium

back side metal contact

High doping is desirable in order to get Ohmic contacts and to reduce the series

resistance of the transistor to reduce circuit RC delays.

f) When the gate of a NMOS transistor is at zero volts, the source-channel-drain

region is essentially two p-n junctions, one between the source and substrate and

the second between the substrate and drain. Why don’t we worry about this

acting like a BJT since the “base” width (source to drain distance) is much less

than the minority carrier diffusion length, one of the criteria for making a good

BJT.

These so-called parasitic BJT’s can be formed in MOSFET circuits and cause big

problems such as latch-up that can lead to catastrophic failures (melting, explosions,

fires, etc). However, in most MOSFET applications, the source and substrate are

connected together thus preventing any carrier injection into the “base” region

between the source and drain and avoiding accidental BJT’s.

g) In the formulas that I used in class for the threshold voltage of a MOSFET, a

term, 2

B

, appears. Even though, I could have simplified the expression to just

write it in terms of 

B

, I always left it as 2

B

instead. What is the significance of

B

B

represents the distance from the intrinsic level to the Fermi level in the

semiconductor substrate in equilibrium. It is a measure of how p-type or n-type that

the substrate is. When the electric field from the gate causes the channel region to

invert from n to p or vice versa, we say that it is inverted if the surface is as p-type as

the substrate was n-type before inversion (or vice versa). Thus 2 

B

is the potential

required to invert the surface of the semiconductor originally characterized by 

B

h) Why is the spectral width of the output of semiconductor lasers always than that

for LED’s made from the same materials?

The “natural” spectral width of the semiconductor is due to the population

distributions of electrons and holes in the semiconductor and usually has a width of 2

or 3 kT. An LED will create light with this “natural” spectral width. A laser

requires feedback in order to sustain the population inversion necessary for lasing.

One form of this feedback is the Fabry-Perot interferometer formed by the cleaved

mirrors on the laser diode. Feedback is only achieved at those wavelengths that

support standing waves in the Fabry-Perot structure and are within the “natural”

spectral width of the material. Therefore, the output of the laser will only be a

portion of the “natural” spectral output of the material and will always be narrower

than the LED output from the same material. This is one way to tell a laser from an

LED.

i) For a photodiode, we need a sufficiently wide depletion layer to absorb as much

of the incoming light as possible, but not too wide to limit the frequency response

of the detector. How would you determine the optimum depletion layer width for

detecting an incoming optical signal which is modulated at 10 GHz?

The speed-limiting factor for the photodiode will be the transit time for the carriers

once created by the light in the depletion region. The carriers can move at a

maximum velocity of about 10

7

cm/sec (thermal velocity) no matter how big the built-

in or applied electric field is. So to detect a 10 GHz signal, the transit time must be

less than the period of the signal (

-

sec). The maximum distance that can be

traveled by the carriers in that time is 10

7

cm/sec*

-

sec=

-

cm or 10μm.

j) If you were designing a silicon p-n junction solar cell, would you want to use high

or low doping concentrations for the n and p regions? Explain.

When designing a solar cell, you would want to convert as much light to electricity as

possible. Therefore, you would like to have a wide depletion width and long minority

carrier diffusion length on both sides of the junction since this defines the sensitive

region of the solar cell. Both of these would indicate low doping levels. However,

doping shouldn’t be too low since the series resistance would be increased for the

quasi-neutral regions.

Bonus : Did you fill out an end-of-course survey for ECE 663? (5 points)

Thank You.