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An overview of the framework for parallel processing, focusing on the shared address space and message passing models. The shared address space model defines communication and programming in parallel architecture through shared memory and virtual address spaces. In contrast, the message passing model uses library calls for communication and a multiprogramming model for conducting multiple jobs without i/o communication simultaneously.
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Shared Address Space Architecture (for Decentralized Memory Architecture)
(for Decentralized Memory Architecture)
Data size is defined as: byte, word, ... or cache blocks
Uses virtual memory to map virtual to local or remote physical
Processes on multiple processors are time shared
Multiple private address spaces offer message passing multicomputer via separate address space
Shared Address Space Architecture Programming Model
Shared Address Space Architecture Programming Model
Multiple processes can overlap, but ALL threads share a process address space, i.e., portions of address spaces of processes are shared; and
writes to shared address space by one thread are visible to reads of all threads in other processes as well
There exist number of shared address space architectures
Shared Address Space Architecture
The main frame architecture was motivated by multiprogramming
As shown here, it extends crossbar for processor interface to memory modules and I/O
Initially this architecture was limited by processor cost; but, later by the cost of crossbar
IBM S/390 (now z-Server) is typical example of cross-bar architecture
However, the bus is bandwidth bottleneck as sharing is limited by Bandwidth when we add processors, I/O
Furthermore, caching is key to the coherence problem – we will talk about this later
The typical example of SMP architecture is Intl Pentium Pro Quad
All processors are on one side of the network and all memories on the other side
As we have notice that in the cross-bar architecture the major cost is of interconnect and in SMPs bus bandwidth is the bottleneck
This architecture offers solution to both the problems through its scalable interconnect network where the bandwidth is scalable
However, the interconnect network has larger access latency; and
caching is key to the coherence problem
