February 22, 2006 page 1 S. Derenzo
Solutions for Midterm #1 - EECS 145M Spring 2006
1When the input number changes in more than one bit, it is impossible for both bit switches
to change exactly at the same time. During the brief time between the first switch change and
the last switch change, an erroneous voltage will be produced.
[4 points off for settling time and no mention of bit changes]
[2 points off for not stating that the bits cannot change simultaneously]
2.1
µcomput
16-bit
digital
output
port
12
D/A
converter
S/H
S/H
S/H
S/H
R1
R3
L1
L3
A0
R2
R4
L2
L4
R1, R3, L1, and L3 are digital control lines to S/H amps
[2 points off for using only two S/H amps, a design that does not update both left and right
within << 1 µs]
2.2
1start loop with i = 1, write HOLD to L3 and R3
2write left[i] to 12 bits of digital output port, write HOLD to R1, L3 and R3 and write
SAMPLE to L1
3write left[i] to 12 bits of digital output port, write HOLD to L1, R1, L3, and R3
Note: this hold command takes effect 1 µs after the new D/A input – much longer than its
100 ns settling time.
4write right[i] to 12 bits of digital output port, write HOLD to L1, L3 and R3, and write
SAMPLE to R1
5write right[i] to 12 bits of digital output port, write HOLD to L1, R1, L3, and R3
6write HOLD to L1 and R1, and write SAMPLE to L3 and R3 (12 bit input to D/A does not
matter)
7write HOLD to L1 and R1, L3 and R3 (12 bit input to D/A does not matter)
8wait until a total of 25 µs (1000 cycles of the 25 ns clock) have passed in the loop
9set i = i + 1 and go back to step 2 until all values are exhausted
[3 points for not accounting for all 16 bits during the first four write operatons.]
[3 points off if not 40 kHz] [3 points off if left and right updates not simultaneous]
[3 points off if analog outputs not glitch free]
2.2 (3600 s/hr) x (2 hr) x (2 bytes per word) x (2 channels) x(40,000 Hz) = 1152 Mbytes =
9.216 Gbits of storage.
6.912 Gbits was also accepted, assuming efficient packing of 12 bit data
