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By making this separation we can

allow an instruction:

• to execute and
• to bypass its result to other

instructions

without …………….. Cont’d

Hardware Based Speculation: Basics

without allowing the instruction to

perform any update that cannot be

undone,

until we know that the instruction

is no longer speculative

Hardware Based Speculation: Basics

This shows that

The basic idea behind implementing

the speculation is

to allow instructions to

execute out-of- order

but force them to

commit in-order

Hardware Based Speculation: Basics

In a single issue five stage pipeline: we can ensure that instructions are committed in- order, simply by moving writes to the end of the pipeline

Because

when we add speculation, we need to separate the process of completing execution and instruction-commit, as the instructions may finish execution considerably before they are ready to commit

Hardware Based Speculation: Implementation

Modified hardware including ROB

Modified Hardware

Here, the reorder buffer can be

operand source, if value not yet

committed

Once operand commits, result

is found in register file

Modified Hardware - Explanation

Instruction results commit to register set in- order

If ROB is implemented as a queue then

it is simple to Undo speculated instructions on mispredicted branches

or on

exceptions just requires throwing away uncommitted entries

Exceptions are not recognized until

an instruction becomes ready to

commit

The figure shows the Tomasulo’s

hardware structure including the

ROB

Extended Tomasulo’s Pipe

Here, the basic structure of a MIPS FP

unit, using Tomasulo’s algorithm is

extended to handle speculation.

The mechanism may be further

extended to multiple issue by making

CDB wider to allow for multiple

completions per clock.

Explanation

Extended Tomasulo’s Pipe

Here, the reorder buffer(ROB)

provides additional buffer,

same way as in reservation

station in Tomasulo’s, that

extend the register set.

In Tomasulo’s approach ,

once an instruction writes its

result, any subsequently issued

instructions will find the result in

the register file.

Explanation .. Cont’d

Whereas, in speculation the register

file is not updated until the instruction

commits –

Thus the ROB supplies operands in the

interval between completion of

instruction execution and instruction

commit.

Explanation .. Cont’d

1. Instruction Type field

It indicates whether:

• The instruction is a branch and has no destination,
• The instruction is a store, which has a memory address destination) , or
• The instruction is a register operation, ALU operation or load, which has register destinations.

Reorder Buffer Fields

2. Destination field

It supplies:

• the register number ( for load and ALU operation) or
• the memory address (for stores) where the instruction result should be written.

Reorder Buffer Fields