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This course focuses on quantitative principle of computer design, instruction set architectures, datapath and control, memory hierarchy design, main memory, cache, hard drives, multiprocessor architectures, storage and I/O systems, computer clusters. This lecture includes: Multiple, Issue, Speculation, Processor, Iterations, Execution, Dynamically, Machines, Loop
Typology: Slides
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Let us consider two tables, for the first three iterations of this loop, for machines with and without speculations The first table shows time of issue, execution, and writing result for two - issue dynamically scheduled processor, without speculation.
Explanation con’t…
Note that the L.D following the BNE cannot start execution earlier, because it must wait until the branch outcome is determined.
This type of program with data dependent branches that cannot be resolved earlier, shows evaluation allow multiple instructions to execute in the same clock cycle.
Explanation con’t…
The second table shows the time of issue, execution and writing result for a dual- issue version of our pipeline with speculation.
Note that the L.D following the BNE can start execution early because it is speculative.
Explanation con’t… Comparing the two tables, note that The third branch in the speculative processor
while in non-speculative processor
That is,
the non-speculative pipelines are falling behind the issue rate rapidly
Now, we will talk about the exceptional situations which may arise when executing a program using dynamic scheduling and how the structure with hardware-based speculation considers these exceptions
We know that the dynamic scheduling without speculation, allows to complete execution out-of-order, where as the structure with speculating-hardware commits in-order
Exceptions to Hardware-based speculation
Therefore, if an exceptional situation occurs while exacting an instruction, the ROB in structure with speculation doesn’t commit and handle exceptions Let us reconsider the execution of our first example program using Tomasulo’s structure with speculation and without speculation
- insert table 3.
Exceptions to Hardware-based speculation
Exceptions to Hardware-based speculation
Furthermore, the exceptions are handled not recognizing then until it is ready to commit
This may be explained by considering our earlier example of the execution of a loop
Loop: L.D F0,0(R1) MUL.D F4,F0,F S.D F4,0(R1) DADDUI R1,R1,# - BNE R1,R2, LOOP ;branch if R1=R
Exceptions to Hardware-based speculation
Summary
The focus of our today’s discussion has been the Tomasulo’s hardware modification to handle execution using speculation, i.e.,
Speculating on the outcome of branches to avoid control hazards, which prevent us from starting the next operation before we know whether the branch was correctly predicted or not
Summary
The Main idea is to allow execution of a branch instruction, predicted taken, such that there are no consequences if branch is not actually taken
Further, we don’t want a speculative instruction to cause exceptions which stop programs
Software generated interrupt or memory violation are typical examples of exceptions
