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Homework 1 Solution
CDA 5155: Fall 2008
- [10 points] You are the product manager for a 4-core processor. The chip has an area of 280 mm^2 , with a defect rate of 0.59 defects per cm^2 and α=4. In this problem, we can view the yield as a probability of no defects occurring in a certain area given the defect rate. Assume defects on different cores occur independently. The die of each chip is entirely occupied by four identical cores.
a. What is the probability that a core has no defect? (Hint: for each chip, use the yield equation on page 22 to calculate the probability that it has no defect on its die. Also notice that there are 4 cores on it.) b. What is the probability that a chip has one or two defected cores (but not more than that)? c. Given your answers to a) and b), what is the number of chips with 2 or 3 working cores you will get for every 4 core chip with no defect? d. Since the yield is so poor, it might make sense to sell two sets of chips: one with 4 working cores and one with at least 2 working cores. If you sell your 4-core chips for $150 each, the 2-core chips for $100 each, you need $80 to manufacture and test each chip and your research and development budget was 200 million, how many processors would you need to sell in order to recoup costs?
Solution： a) Yield of a single die = (1 + (0.59×2.80)/4 ) -4= 0. Probability that a core has no defect = (0.25) 1/4= 0. b) Probability that a core has some defect = 1 − 0.71 = 0. Probability that a chip has one defected core = 0.29 × 0.71^3 × 4 = 0. Probability that a chip has two defected cores = 0.29^2 × 0.71^2 × 6 = 0. Probability that a chip has one or two defected cores = 0.25 + 0.42 = 0. c) 0.67/0.25 = 2. d) 3.68*200000000/(150 + 2.68 × 100 – 3.68 × 80) = 5.95 million chips Note that if you think $80 means we need $80 to fabricate each chip and calculate based on that, the result (about 7.6 million) is also correct.
- [10 points] Use the table shown below to solve the following questions:
Processors (Chip) Num of Cores Memory Performance
Processor Performance Intel Core2 Quad Q9450 4 4726 3645 AMD Phenom 9500 4 4103 2088 Intel Core2 Duo E840 2 4097 2032 AMD Athlon 64 X2 6400 + 2 4386 1285 Intel Pentium 4 3.40GHz 1 3340 523 AMD Athlon 64 3800+ 1 2489 485 Processor X 1 8000 500
a. Create a table similar to the given table, except express the results as normalized to the AMD Athlon 64 X2 6400+ for both memory performance and processor performance.
b. Calculate the arithmetic mean of the performance of each processor using both the original performance and your normalized performance.
c. Given the answer from part b), are there any conflicting conclusions you can make?
Solution：
a)
Processors (Chip) Num of Cores
Memory Processor
Intel Core2 Quad Q9450 4 1.078 2.
AMD Phenom 9500 4 0.935 1.
Intel Core2 Duo E840 2 0.934 1.
AMD Athlon 64 X2 6400 + 2 1.000 1.
Intel Pentium 4 3.40GHz 1 0.762 0.
AMD Athlon 64 3800+ 1 0.567 0.
Processor X 1 1.824 0.
Solution：
a) If we use only one processor, the maximum average performance is 500MIPS. If we use two processors, the maximum average performance is 1/(0.8/300+0.2/600)=333(MIPS). Therefore, the system should run in single processor mode. The average performance is 500MIPS. b) If 95% of the application is parallelizable, then the maximum average performance in the dual processor mode is changed to 1/(0.05/300+0.95/600)=571(MIPS). The speedup is 571/500=1. c) For design a), MTTF = 109/100= For design b), the system spends 0.05/(0.05+0.95/2)=9.5% of its running time using only one processor. It spends 1-9.5%=90.5% of its running time using two processors.
The system FITb = 1000.095+0.905(1002)=190. MTTF = 109/190.5=5.2 Therefore, the first one is more reliable.
- [10 points] Assume that values A, B, C and D reside in memory. Write the code sequence for
D=A + (B * C) - (A * B)
for four instruction-set architectures: i) Stack, ii) Accumulator, iii) Register-memory and iv) Register- register (Load-Store). (These four architectures are shown in Figure B.1 on page B-4 of the Appendix B). Do not perform any scheduling or optimizations!
Solution：
i) Stack
ii) Accumulator
iii) Register-memory
iv) Register-register Push A Load A Load R1 A Load R1,A Push B Mul B Mul R2,R1,B Load R2,B Add Store AB Load R3 B Load R3,C Push B Load B Mul R4,R3,C Mul R4,R1,R Push C Mul C Add R1,R1,R4 Mul R5,R3,R Mul Store BC Sub D,R1,R2 Add R1,R1,R Push A Load A Sub R1,R1,R Add Add BC Store R1,D Sub Sub AB Pop D Store D
- [10 points] Several researchers have suggested that adding a register-memory addressing mode to a load/store machine might be useful. The idea is to replace sequences of
LOAD R1,0(R3) ADD R2,R2,R by ADD R2,0(R3)
Assume the new instruction will cause the clock cycle increase by 10%. Assume, 15% of dynamic instructions are loads and 10% are stores. The new instruction affects only the clock speed and not the CPI.
a. What percentage of the loads must be eliminated for the machine with the new instruction to have at least the same performance?
b. Show a situation in a multiple instruction sequence where a load of R1 followed immediately by a use of R1 (with some type of opcode) could not be replaced by a single instruction of the form proposed.
Solution：
a) Let the percentage of the eliminated loads be x, 1.1*(1-0.15x)< Therefore x should be greater than 60.6% b) LOAD R1, 0(R3) ADD R1, R1, R Or LOAD R1,1(R3) ADD R2, R2, R SUB R3, R2, R
