EECS 388: Computer Systems and Assembly
Language
Homework 5 Solution
1. (20) How many RTI interrupt events must occur to generate
a 15 minute delay assuming the MCLK is operating at
2MHz and the RTR[2:0] bits are set for โ110โ? How do
you set up the RealโTime Interrupt Control Register (RTICTL)
(i.e., enable RTI and set RTI pre-scale) for this purpose?
According to the table on page 229 of your textbook, the period of a
RTI interrupt is set by the MCLK frequency divided by a divisor stored in
RTR[2:0]. Therefore:
RTR[2:0] = โ110โ implies a clock divider of 218.
MCLK = 2 MHz and a divider of 218 implies that the frequency of
RTI interrupts is 7.6294 Hz (2 MHz / 218).
The time delay, or period, between RTI events is thus 1/7.6294
Hz = 0.1311 seconds (because period = 1 / frequency).
Now, if we want a delay of 15 minutes:
15 minutes = 900 seconds.
Number of RTI events for 15 minutes =
o(900 seconds)/(0.1311 seconds per delay) = 6,867.
oThus, it will require about 6,867 RTI events
One must write the appropriate values into the RTICTL in order to
enable interrupts and to set the RTI frequency. The RTICTL register is a
memory-mapped location located at address $0014. The RTIE bit is the
MSB (bit 7), while the RTR[2:0] bits are the least-significant 3 bits (bits
2 through 0).
RTICTL EQU $0014 ; Equate for the address of the RTICTL register
LDAA %10000110 ; RTICTL mask (RTIE =โ1โ, RTR[2:0]
= โ110โ)
STAA RTICTL ; Store the value into RTICTL
2. (15) Textbook, page 291. Advanced problem #4. Change
MCLK to 4 MHz.
