Enhancements to Von Neumann Computer: Timing, Memory, Prediction, and Pipelining, Slides of Digital Logic Design and Programming

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Sequential Logic Design

Lecture

• Agenda

1. Improvements to the von Neumann Stored Program Computer

• Announcements

1. IDEA evaluations

von Neumann Computer

• Bottleneck

• we have seen that the von Neumann computer is serial in its execution of

instructions

• this is good for simplicity, but can limit performance
• there are many techniques to improve the performance of this computer

1) Functional Timing

2) Memory Architecture

3) Algorithmic Branch Prediction

4) Pipelines

• Functional Timing
  • a delay (or phase) can be added to the clock that the B-register sees. This creates a single-shot

structure which executes in 1 cycle

D Q CLKB D Q CLK

A B

(from controller) LOAD AQ BQ

A(0) A(1)

A(0)

t (^) phase CLKA tphase t (^) CQ t (^) CQ

• Functional Timing
  • this allows multiple register transfers in one clock cycle

ex) Clock 1 : MAR <= PC

Clock 2 : IR <= MAR

PC <= PC + 1

• it still takes two clock edges, but due to phasing, these edges occur within one system clock cycle
• note that control signals going to the phased block need to be phased also:
  • IR_Load
  • PC_Inc
• the phase timing needs to wait long enough for combinational logic signals to propagate

and for Register delays (Setup/Hold/tCQ)

• 3-Algorithmic Branch Predicting
• algorithms can be developed to “predict” a potential branch
• this would allow the memory controller to load up a portion of Cache with the code that could

be potentially executed if the branch was taken

ex) Loop:

DECX

BEQ Loop

BRA Compute

• The code for “Loop” is loaded into Cache because it will probably be executed

more than once

• the code residing at “Compute” will be executed (once the loop ends), so it is

loaded into an unused portion of Cache in parallel to the execution of “Loop”

• Multi-Level Cache
  • Multiple levels of cache can be used to try to reduce memory access time even further
    • L1 (Level 1) cache – smallest and fastest
    • L2 (Level 2) cache - a little larger and a little slower than L
      • but still faster than DRAM
  • the CPU will always try to execute out of the fastest RAM
  • the CPU will

1) check whether the code to be executed is in L1 cache

2) if not, check whether the code is in L2 cache

3) if not, the memory controller will load L1 with the code from DRAM

• NOTE: cache will have both Instruction and Data storage