Download WGU C952 230+ (Latest 2025-2026 Edition) 100% Verified Q&A + Answer Key Solutions and more Exams Information Technology in PDF only on Docsity!
WGU C
230+
(Latest 2025-2026 Edition) 100% Verified Q&A + Answer Key Solutions VERIFIED ANSWERS
Question 1 Register File Correct Answer A state element that consists of a set of registers that can be read and written by supplying a register number to be accessed. provides 1024 scalar 32-bit registers for up to 64 threads. Question 2 machine language Correct Answer The language made up of binary-coded instructions that is used directly by the computer Question 3 system software Correct Answer The set of programs that enables a computer's hardware devices and application software to work together; it includes the operating system and utility programs. Question 4 operating system Correct Answer (computer science) software that controls the execution of computer programs and may provide various services Question 5 Assembly Language Correct Answer Programming language that has the same structure and set of commands as machine languages but allows programmers to use symbolic representations of numeric machine code.
IBM 360/
Correct Answer
Introduced many new concepts, including dynamic detection of memory hazards, generalized forwarding, and reservation stations. Tomasulo's algorithm
The internal organization of the 360/91 shares many features with the Pentium III and Pentium 4, as well as with several other microprocessors. One major difference was that there was no branch prediction in the 360/91 and hence no speculation. Another major difference was that there was no commit unit, so once the instructions finished execution, they updated the registers.
Question 7
Dynamic Random Access Memory (DRAM)
Correct Answer
Memory built as an integrated circuit; it provides random access to any location. Access times are 50 nanoseconds and cost per gigabyte in 2012 was $5 to $10.
Multiple DRAMs are used together to contain the instructions and data of a program. In contrast to sequential access memories, such as magnetic tapes, the RAM portion of the term DRAM means that memory accesses take basically the same amount of time no matter what portion of the memory is read.
Modern DRAMS consist of rows in each bank
Question 8
frame buffering
Correct Answer
A portion of RAM containing a bitmap that drives a video display. It is a memory buffer containing a complete frame of data.
The image to be represented onscreen is stored in the frame buffer, and the bit pattern per pixel is read out to the graphics display at the refresh rate. The animation below shows a frame buffer with a simplified design of just 4 bits per pixel.
Question 9
Datapath
Correct Answer
The component of the processor that performs arithmetic operations
Question 10
Control
Correct Answer
The component of the processor that commands the datapath, memory, and I/O devices according to the instructions of the program.
Magnetic disk
Correct Answer
Also called hard disk. A form of nonvolatile secondary memory composed of rotating platters coated with a magnetic recording material. Because they are rotating mechanical devices, access times are about 5 to 20 milliseconds and cost per gigabyte in 2012 was $0.05 to $0.
Question 19
Main memory
Correct Answer
Also called primary memory. Memory used to hold programs while they are running; typically consists of DRAM in today's computers.
Question 20
Secondary memory
Correct Answer
Nonvolatile memory used to store programs and data between runs; typically consists of flash memory in PMDs and magnetic disks in servers.
Question 21
Flash memory
Correct Answer
A nonvolatile semiconductor memory. It is cheaper and slower than DRAM but more expensive per bit and faster than magnetic disks. Access times are about 5 to 50 microseconds and cost per gigabyte in 2012 was $0.75 to $1.00.
Question 22
Single Instruction Single Data (SISD)
Correct Answer
A uniprocessor
Question 23
Multiple Instruction Multiple Data (MIMD)
Correct Answer
A multiprocessor.
Question 24
Single Program, Multiple Data Streams (SPMD)
Correct Answer
The conventional MIMD programming model, where a single program runs across all processors.
Single Instruction Stream, Multiple Data Streams (SIMD)
Correct Answer
The same instruction is applied to many data streams, as in a vector processor.
Question 26
Data-level parallelism
Correct Answer
Parallelism achieved by performing the same operation on independent data
Question 27
vector-based code
Correct Answer
Question 28
conventional code
Correct Answer
Question 29
LEGv
Correct Answer
assembly instructions
Question 30
multimedia extensions (MMX)
Correct Answer
An expanded set of instructions supported by a processor that provides multimedia-specific functions.
Question 31
data hazard (pipeline data hazard)
Correct Answer
When a planned instruction cannot execute in the proper clock cycle because data that is needed to execute the instruction are not yet available.
Question 32
forwarding (bypassing)
Correct Answer
A method of resolving a data hazard by retrieving the missing data element from internal buffers rather than waiting for it to arrive from programmer-visible registers or memory
Memory hierarchy
Correct Answer
A structure that uses multiple levels of memories; as the distance from the processor increases, the size of the memories and the access time both increase.
Question 41
Block (or line)
Correct Answer
The minimum unit of information that can be either present or not present in a cache.
Question 42
Hit rate
Correct Answer
The fraction of memory accesses found in a level of the memory hierarchy.
Question 43
Miss rate
Correct Answer
The fraction of memory accesses not found in a level of the memory hierarchy
Question 44
miss penalty
Correct Answer
The time required to fetch a block into a level of the memory hierarchy from the lower level, including the time to access the block, transmit it from one level to the other, insert it in the level that experienced the miss, and then pass the block to the requestor.
Question 45
Hit time
Correct Answer
The time required to access a level of the memory hierarchy, including the time needed to determine whether the access is a hit or a miss.
Question 46
Parallelization
Correct Answer
consist of dividing a program into separate components that run in parallel on individual computers in the cluster
superscalar
Correct Answer
Technique primarily associated with hardware.
Functional units (ALU, Floating Point Unit, Load/Store Unit) are duplicated in the pipeline of a superscalar processor which allows the hardware to issue multiple instructions to each unit simultaneously.
Question 48
ARM architecture
Correct Answer
can support 16-bit
Question 49
Amdahl's Law
Correct Answer
A formula used to find the maximum improvement possible by improving a particular part of a system. In parallel computing, Amdahl's law is mainly used to predict the theoretical maximum speedup for program processing using multiple processors
Question 50
multiprocessor
Correct Answer
A term used to refer to a computer with more than one CPU.
Question 51
Uniform Memory Access (UMA)
Correct Answer
A multiprocessor in which latency to any word in main memory is about the same no matter which processor requests the access.
Question 52
Non-Uniform Memory Access (NUMA)
Correct Answer
Varying system memory access times, because of system hardware.
Question 53
loop unrolling
Correct Answer
A technique to get more performance from loops that access arrays, in which multiple copies of the loop body are made and instructions from different iterations are scheduled together.
RAID 5
Correct Answer
Disk striping with parity. RAID-5 uses three or more disks and provides fault tolerance.
Question 62
RAID 6
Correct Answer
Disk striping with parity. RAID-6 uses four or more disks and provides fault tolerance. It can survive the failure of two drives.
Question 63
silicon crystal ingot
Correct Answer
A rod composed of a silicon crystal that is between 8 and 12 inches in diameter and about 12 to 24 inches long.
Question 64
wafer
Correct Answer
A slice from a silicon ingot no more than 0.1 inches thick, used to create chips.
Question 65
Instruction Set Architecture (ISA)
Correct Answer
Also called architecture. An abstract interface between the hardware and the lowest-level software that encompasses all the information necessary to write a machine language program that will run correctly, including instructions, registers, memory access, I/O, and so on
Question 66
Application Binary Interface (ABI)
Correct Answer
The user portion of the instruction set plus the operating system interfaces used by application programmers. It defines a standard for binary portability across computers.
Question 67
Transistor
Correct Answer
An on/off switch controlled by an electric signal
very large-scale integrated (VLSI) circuit
Correct Answer
A device containing hundreds of thousands to millions of transistors.
Question 69
silicon
Correct Answer
A natural element that is a semiconductor
- Excellent conductors of electricity (using either microscopic copper or aluminum wire)
- Excellent insulators from electricity (like plastic sheathing or glass)
- Areas that can conduct or insulate under special conditions (as a switch)
Question 70
Semiconductor
Correct Answer
A substance that can conduct electricity under some conditions
Question 71
Die
Correct Answer
The individual rectangular sections that are cut from a wafer, more informally known as chips.
Question 72
complementary metal-oxide semiconductor (CMOS)
Correct Answer
Dominant technology for integrated circuits
Question 73
LEGv
Correct Answer
Assembly Language
Question 74
LEGv8 word
Correct Answer
A natural unit of access in a computer, usually a group of 32 bits
LEGv8 LDUR
Correct Answer
The sum of the constant portion of the instruction and the contents of the second register forms the memory address
The U in LDUR stands for unscaled immeditate
Question 82
base address
Correct Answer
starting address of an array in memory (5000 below)
Question 83
base register
Correct Answer
register that holds an array's base address (X22 below)
Question 84
offset
Correct Answer
a constant value added to a base address to locate a particular array element (8 below)
Question 85
Big Endian
Correct Answer
A CPU or memory architecture in which the most significant byte is stored at the lowest memory address.
Question 86
store register
Correct Answer
instruction complementary to load. It copies data from register to memory.
the format is similar to load; name of the operation, followed by the register to be stored, then the base register, and finally the offset to select the array element.
Question 87
LEGv8 STUR
Correct Answer
store register
spilling register
Correct Answer
The process of putting less frequency used variables (or those needed later into memory)
Question 89
reservation station
Correct Answer
A buffer within a functional unit that holds the operands and the operation.
Question 90
commit unit
Correct Answer
The unit in a dynamic or out-of-order execution pipeline that decides when it is safe to release the result of an operation to programmer-visible registers and memory.
Question 91
Reorder Buffer
Correct Answer
The buffer that holds results in a dynamically scheduled processor until it is safe to store the results to memory or a register.
Question 92
out-of-order execution
Correct Answer
A situation in pipelined execution when an instruction blocked from executing does not cause the following instructions to wait.
Question 93
in-order commit
Correct Answer
A commit in which the results of pipelined execution are written to the programmer-visible state in the same order that instructions are fetched.
Question 94
VLIW
Correct Answer
A style of instruction set architecture that launches many operations that are defined to be independent in a single wide instruction, typically with many separate opcode fields
virtual memory
Correct Answer
A technique that uses main memory as a "cache" for secondary storage
The address is broken into a virtual page number and a page offset
Question 103
physical address
Correct Answer
An address in main memory.
Question 104
Protection
Correct Answer
A set of mechanisms for ensuring that multiple processes sharing the processor, memory or I/O devices cannot interfere, intentionally or unintentionally, with one another by reading or writing each other's data. These mechanism also isolate the operating system from a user process.
Question 105
page
Correct Answer
a virtual memory block.
all virtual memory system relocate the program as a set of fixed-size blocks
Question 106
page fault
Correct Answer
a virtual memory miss
Question 107
virtual address
Correct Answer
An address that corresponds to a location in virtual space and is translated by address mapping to a physical address when memory is accessed.
page table
Correct Answer
The table containing the virtual to physical address translations in a virtual memory system. The table, which is stored in memory, is typically indexed by the virtual page number; each entry in the table contains the physical page number for that virtual page if the page is currently in memory.
indexed by the page number from the virtual address
Question 109
swap space
Correct Answer
The space on the disk reserved for the full virtual memory space of a process
Question 110
Reference Bit (Use Bit or Access Bit)
Correct Answer
A field that is set whenever a page is accessed and that is used to implement LRU or other replacement schemes.
ARMv8 calls it an access bit
Question 111
Techniques for reducing total max storage required
Correct Answer
- Keep a limit register that restrict the size of the page table for a given process and add more entries as needed.
- A limit register for each segment specifies the current size of the segment, which grows in units of pages. This type of segmentation is used by many architectures, including ARMv8 and MIPS. Unlike the type of segmentation discussed in a previous elaboration, this form of segmentation is invisible to the application program, although not to the operating system. This does not work when the address space is used sparsely rather than contiguous.
- Apply a hashing function to the virtual address so that the table need to be only the size of the number of physical pages in the main memory. AKA inverted page table. Lookup process can be more complex because it is not indexed
- Allow the page tables to be paged. It works by allowing the page tables to reside in the virtual address space.
- Multiple levels of page tables and is the solution that ARMv8 uses to reduce the memory footprint of address translation. This scheme allows the address space to be used in a sparse fashion (multiple noncontiguous segments can be active) without having to allocate the entire page table. Useful with very large address spaces and in software systems that require noncontiguous allocation. The primary disadvantage of this multi-level mapping is the more complex process for address translation.
TLB events combination
Correct Answer
+-------+-------------+-------+------------+ | TLB | Page table | Cache | Result | +-------+-------------+-------+------------+ | Hit | Hit | Miss | Possible | | Miss | Hit | Hit | Possible | | Miss | Hit | Miss | Possible | | Miss | Miss | Miss | Possible | | Hit | Miss | Miss | Impossible | | Hit | Miss | Hit | Impossible | | Miss | Miss | Hit | Impossible | +-------+-------------+-------+------------+
Question 119
virtually addressed cache
Correct Answer
A cache that is accessed with a virtual address rather than a physical address
Does not use the TLB
Question 120
Aliasing
Correct Answer
A situation in which two addresses access the same object; it can occur in the virtual memory when there are two virtual addresses for the same physical page
Question 121
Physically addressed cache
Correct Answer
A cache that is addressed by a physical address.
Question 122
context switch
Correct Answer
A changing of the internal state of the processor to allow a different process to use the processor that includes saving the state needed to return to the currently executing process.
Question 123
syscall
Correct Answer
Generates a system call exception that transfers control to the processor and allows access to a dedicated location in supervisor code space. The process returns to user mode via the RET instruction.
L1 cache (primary cache)
Correct Answer
a cache for a cache
Question 125
L2 cache
Correct Answer
A cache for main memory
It is faster than memory, but tends to be larger and slower than the L1 cache
Question 126
Virtual machines
Correct Answer
Developed in the mid-1960s.
Benefits: Managing software Managing hardware
Question 127
virtual machine manager (VMM)
Correct Answer
Hypervisor
usually, run in system mode while guest VM run in user mode.
hardware = host VMs = guest
It determines how to map virtual resources to physical resources.
It is also much smaller than a traditional OS; the isolation portion of a VMM is only 10,000 lines of code
Question 128
Instruction Set Architecture (ISA)
Correct Answer
The part of the computer architecture related to programming, including the native data types, instructions, registers, addressing modes, memory architecture, interrupt and exception handling, and external I/O.
