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Input – Output Design and

Organization^ Chapter 8

Input/Output Problems

^ Wide variety of peripherals^ ■^ Delivering different amounts of data^ ■^ At different speeds^ ■^ In different formats
^ All slower than CPU and RAM
^ Need I/O modules

Generic Model of I/O Module

External Devices

^ Human readable^ ■^ Screen, printer, keyboard
^ Machine readable^ ■^ Monitoring and control
^ Communication^ ■^ Modem^ ■^ Network Interface Card (NIC)^ ■^ Serial Port^ ■^ Parallel Port

I/O Module Function

^ Control & Timing
^ CPU Communication
^ Device Communication
^ Data Buffering
^ Error Detection

I/O Steps

^ CPU checks I/O module device status
^ I/O module returns status
^ If ready, CPU requests data transfer
^ I/O module gets data from device
^ I/O module transfers data to CPU
^ Variations for output, DMA, etc.

Basic Concepts ©Javaid Khurshid

^ The Figure below shows a simple arrangement forconnecting the processor and the memory in agiven computer system to an input device and anoutput device.
^ A single bus consisting of the required address,data, and control lines is used to connect thesystem's components.

Basic Concepts

^ There exists a big difference in the rate at which aprocessor can process information and those ofinput and output devices.
^ A simple way of communication between theprocessor and I/O devices, called the

I/O protocol

requires the availability of the input and outputregisters.
A mechanism according to which the processor canaddress those input and output registers must beadopted.
More than one arrangement exists to satisfy theabove mentioned requirements.

Basic Concepts: Shared I/O
In the first arrangement, I/O devices are assignedparticular addresses, isolated from the addressspace assigned to the memory.
The Execution of an

Input Instruction

at an input

device address will cause the character stored inthe^ Input Register

of that device to be transferred to a specific register in the CPU.
Similarly, the execution of an

Output Instruction

at

an output device address will cause the characterstored in a specific register in the CPU to betransferred to the

Output Register

of that output

device.
This arrangement is called

Shared I/O.

Basic Concepts: Shared I/O arrangement

Basic Concepts: Memory-Mapped I/O
^ The second possible I/O arrangement is to dealwith^ Input

and^ Output Registers

as if they are

regular memory locations.
In this case, a

Read^ operation from the address corresponding to the

Input Register

of an input

device, e.g.,

Read Device6,

is equivalent to

performing an

Input Operation

from the input

register in Device #6.
Similarly, a

Write^ operation to the address corresponding to the

Output Register

of an output

device, e.g.,

Write Device9,

is equivalent to

performing an

Output Operation

into the output

register in Device #9.
This arrangement is called

Memory-Mapped I/O

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©Javaid Khurshid

Basic Concepts: Memory-mapped I/O

arrangement:

^ Programmed I/O
^ Interrupt-Driven I/O

Programmed I/O ©Javaid Khurshid

^ Example of an 8 I/O device connection to a processor