Project Topics and Compiler Optimizations in Computer Architecture, Study notes of Computer Architecture and Organization

Various project topics and compiler optimization techniques in the field of computer architecture. The project topics include trading reliability for energy, application-specific instruction processors, low-density parity check codes, and simultaneous multithreading. The compiler optimization techniques discussed include high-level, local, and global optimizations, register allocation, and instruction scheduling. The document also highlights the role of a compiler and the anatomy of a compiler.

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Chapter 2
Computer Architecture
Venkatesh Akella
EEC 270
Winter 2005
Chapter 2
Project Topics
1. Trading Reliability for Energy : Voltage Overscaling
in Data Caches, especially in media applications
2. ASIP - Application Specific Instruction Processor
for a given domain - streaming, packetization,
arithmetic coding, error correction/detection
3. Application Specific Loop Processor - a simple
programmable vector co-processor for ARM and
implement using Tensilica, SimpleScalar for
multimedia or message passing algorithms (LDPC
decoding), focus on programmable memory access
unit and smaller bitwdith operations
4. Network processors for multimedia over wireless ad-
hoc networks.
5. Processors for Sensor Networks
6. Low Density Parity Check Codes - Programmable
Architectures
7. Simultaneous Multithreading and dynamic resource
management
Chapter 2
Project Topics
Embedded Processors
ASIP
ASLP
Voltage speculation to save energy
Overclocking data caches
Reliability vs energy
Multithreading for dynamic resource management
Low Density Parity Check Codes
High Speed - interconnection networks
HW/SW Codesign
Networking Processors
Sensors
Multimedia Packet Scheduling
Chapter 2
Instruction Set Design – Principles and
Examples
Execution Time = IC * CPI * Tc
IC = Dynamic Instruction Count
Instruction Set influences IC, CPI
Desktop – Int/FP – power/codesize not important
Server - Integer – No FP – string manipulation imp
Embedded – Cost, Power, Real time – smaller
bitwdith
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Chapter 2

Computer Architecture

Venkatesh Akella EEC 270 Winter 2005 Chapter 2

Project Topics

  1. Trading Reliability for Energy : Voltage Overscaling in Data Caches, especially in media applications
  2. ASIP - Application Specific Instruction Processor for a given domain - streaming, packetization, arithmetic coding, error correction/detection
  3. Application Specific Loop Processor - a simple programmable vector co-processor for ARM and implement using Tensilica, SimpleScalar for multimedia or message passing algorithms (LDPC decoding), focus on programmable memory access unit and smaller bitwdith operations
  4. Network processors for multimedia over wireless ad- hoc networks.
  5. Processors for Sensor Networks
  6. Low Density Parity Check Codes - Programmable Architectures
  7. Simultaneous Multithreading and dynamic resource management Chapter 2

Project Topics

  • Embedded Processors
    • ASIP
    • ASLP
  • Voltage speculation to save energy
    • Overclocking data caches
    • Reliability vs energy
  • Multithreading for dynamic resource management
  • Low Density Parity Check Codes
    • High Speed - interconnection networks
    • HW/SW Codesign
  • Networking Processors
    • Sensors
    • Multimedia Packet Scheduling Chapter 2

Instruction Set Design – Principles and

Examples

Execution Time = IC * CPI * Tc IC = Dynamic Instruction Count Instruction Set influences IC, CPI Desktop – Int/FP – power/codesize not important Server - Integer – No FP – string manipulation imp Embedded – Cost, Power, Real time – smaller bitwdith

Chapter 2

Overview of the Chapter

  • What are the alternatives and trade-offs?
  • Taxonomy of ISA and quantitative assessment
  • ISA of embedded and DSP processors
  • Role of Compilers and High-level Languages
  • TriMedia and MIPS64 Cases Study Chapter 2

Anatomy of an Instruction

  • Operation
    • Arithmetic
    • Logical
    • Control Flow
    • Procedure Call
  • Operands
    • Type of operands (bit, byte, char, string, float, int)
    • Addressing the operands (Addressing modes)
  • Representation in the memory (encoding)
    • Fixed vs variable
    • Aligned vs unaligned
    • Lilliputian Wars
    • Compressed vs Uncompressed
    • Impacts code size, decode efficiency, Chapter 2

Classifying Instruction Set

Architectures

Chapter 2

Why did Register-Register ISA

survive?

  • Registers are faster than memory
  • Take advantage of principle of locality
  • Flexibility – Consider the expression: (AB) – (BC) – (A*D) There are several ways of evaluating this on a R-R machine but on a stack based machine it is restricted to one order . Code density – registers can be specified with fewer bits than memory addresses . Reduces memory traffic – locality . Amenable for automatic compilation

Chapter 2

Mix of Instructions on TI DSP C54x

MAC 4.6% Move mem-mem16 4.0% Subtract mem16 4.9% Push mem16 5% CALL 5% Add mem16 6.8% Load mem16 9.4% Store mem16 32.2% Instruction Percent Chapter 2

Interesting Questions

  • How many bits for the immediate field?
  • How many registers do I need?
  • What addressing modes to support?
  • What operations to support?
  • Amadahl’s law
  • Make the common case fast
  • Can the compiler use it?
  • Don’t forget, ultimately Execution Time matters – so always look at the impact on IC, CPI and Tc
  • Measure on Real Benchmarks! Chapter 2

Role of a Compiler

  • Today majority of programming is in high-level languages.
  • So, the Instruction set should be amenable for a compiler as a target
  • Case in point – DSP, micro controllers are not which makes software development a nightmare
  • Remember – architecture is a codesign issue, so a smart compiler can help if the architecture exposes some aspects
  • Eg: instruction scheduling to avoid pipeline stalls, hide long latency of memory, use the registers better, avoid recomputation, code size optimization, cache optimization, ……. Chapter 2

Anatomy of a compiler

Chapter 2

Compiler Optimizations

  • High-level optimizations – source level transformations Eg: procedure integration, code inlining
  • Local optimizations – in a basic block, or straight line code Eg: common sub-expression elimination, constant propagation, stack height reduction
  • Global optimizations – across branches Eg: Copy propagation, code motion, loop optimization, unrolling
  • Register allocation
  • Instruction Scheduling Chapter 2

How can the architect help the

compiler writer?

  • Regularity a.k.a orthogonality of instruction set
  • Provide primitives, not solutions
  • Expose the cost of different trade-offs – especially with pipelining and caches this is difficult Eg: how many times should a variable be used before it is better stored in register? Hard to determine? . Provide instructions that bind quantities known at compile time as constants Eg: It is a waste to let the processor interpret a value at runtime that was a compile time constant