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Practice questions related to compiler optimizations and control flow graph analysis. The questions cover topics such as compiler transformations, local optimizations, reaching definitions, live variables, available expressions, and instruction scheduling. Students are asked to build a dag for a code segment, perform control flow analysis, calculate reaching definitions and live variables, and determine available expressions and instruction schedules.
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These 3-address co de instructions may b e used in the follow- ing questions:
3-addr Instruction E ect load R1 x R1 x store x R1 x R add R1 R2 R3 R1 R2 + R sub R1 R2 R3 R1 R2 - R mult R1 R2 R3 R1 R2 * R
(a) How can compiler transformations improve a pro- gram? (b) What do es the compiler need to consider when ap- plying optimizations? (c) What are the di erent scop es of compiler optimiza- tions? What are the tradeo s when considering what scop e of optimizations to use?
(1) a := 1 (2) b := f + a (3) c := a (4) d := f + a (5) e := f + c (6) f := b (7) g := f + a
(a) Build a DAG for the co de.
(a) What are the basic blo cks? (b) What is the control ow graph?
(c) Depth- rst order selects no des in the order they are visited (start by visiting the ro ot no de) and then recursively visiting every child of each no de (if the child has not b een visited b efore). Note that the order in which children are visited is random. What are all the p ossible results of depth- rst traver- sal on the control ow graph? (d) Using depth- rst order, is it p ossible to visit a child b efore its parent? For which depth- rst ordering(s) of the control ow graph do es this o ccur? (e) Postorder selects no des (starting from ro ot) after visiting every child of that no de (if the child has not b een visited b efore). Note that the order in which children are visited is random. What are all the p ossible results of Postorder traver- sal for the control ow graph? (f ) Reverse Postorder simply reverses the no de order- ing found by a Postorder traversal of the graph. What are the p ossible Reverse Postorder traver- sals of the control ow graph? (g) Using Reverse Postorder, is it p ossible to visit a child b efore its parent? Why or why not?
(a) What is the data ow equation for REACH? (b) In what direction is REACH calculated? I.e., do es information ow forwards or backwards in the CFG? (c) Calculate GEN, KILL for each basic blo ck. (d) What is a go o d initial value for REACH for each basic blo ck? (e) Solve the data- ow equations in reverse Postorder. Show your work.
(a) We de ne LIVE(b) for a basic blo ck b to b e the set of live variables at the end of b. What is the data ow equation for LIVE? (b) In what direction is LIVE calculated? I.e., do es in- formation ow forwards or backwards in the CFG? (c) Show GEN, KILL for each basic blo ck. (d) What is a go o d initial value for LIVE for each basic blo ck? (e) Solve the data- ow equations in rPostorder. Show your work.
Available expressions is a data- ow analysis problem whose solution is used to guide global common sub ex- pression. It calculates AVAIL, the expressions available at the b eginning of each basic blo ck. Consider the following co de. Assume that b+c is the only expression of interest:
(a) What is the data- ow equation for AVAIL? (b) Give GEN and KILL (needed by AVAIL) for each basic blo ck. (c) What is a go o d initial value for AVAIL for each basic blo ck? (d) Calculate AVAIL. Show all steps, including values for AVAIL and the order basic blo cks are analyzed.
Prove the following prop erties of lattices:
(a) Show that a b and b c implies a c
(b) Show that a (b ^ c) implies a b
(a) When estimating each of the following sets, tell whether to o-large or to o-small estimates are con- servative. Explain your answer in terms of the in- tended use of information. i. Available expressions ii. Reaching de nitions iii. Live variables (b) What prop erties are necessary to ensure an itera- tive data- ow analysis framework terminates? (c) What prop erties are necessary to ensure an itera- tive data- ow analysis framework terminates with the meet-over-all-paths solution?
2-cycle latency for load 1-cycle latency otherwise
(a) Build the precedence graph for the instructions. Mark dep endences as ow, anti, or output. You can ignore transitive dep endences. (b) Calculate the critical path for the instructions. (c) Schedule the instructions for a single-issue pro ces- sor, using forward list scheduling. Show candidates instructions at each cycle. Prioritize candidates using 1) critical path, 2) latency of instruction, 3) numb er of children. (d) Schedule the instructions as ab ove, for a two-issue VLIW pro cessor. (e) How could you change register assignments to im- prove instruction schedules in the co de?