Intel Cache Safe Technology - Computer Systems Architecture - Lecture Slides, Slides of Computer Architecture and Organization

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OUTLINE

• Introduction
• Key Features
  • Two 64-bit cores (Intel 64 Technology)
  • Hyper-Threading Technology
  • Up to 16 MB of shared L3 (on die cache)
  • Intel Cache Safe Technology
  • Intel Virtualization Technology
  • Demand-Based Switching (DBS) with Enhanced Intel SpeedStep technology
  • High-speed, 3-load, front-side system bus (800 MHz)
• Performance
• References

Introduction

• Up to 60 percent improvement on business processing
  • enterprise resource planning (ERP)
  • supply chain management (SCM)
  • customer relationship management (CRM)
• Up to 70 percent improvement on transaction processing
• Over to twice the performance on e-commerce applications
• Up to 2.8x performance per watt improvement compared to

previous generation.

Mechanical Specifications

• packaged in a Flip-Chip Micro Pin Grid Array 6 (FC-mPGA6) package
• The package components:
• 1. Integrated Heat Spreader (IHS)
• 2. Processor die
• 3. FC-mPGA6 package
• 4. Pin-side capacitors
• 5. Package pin

Key Features

• Hyper Pipelined Technology

• Rapid Execution Engine

• Execution Trace Cache

• Execute Disable Bit

• Package Thermal Specifications

Dual-Core (64-bit Cores)

• combines two independent processors into a single package
• In general, multi-core microprocessors allow a computing device to exhibit some form of thread-level parallelism ( TLP ) (chip-level multiprocessing)
• 64-bit computing
• Run both 32-bit and 64-bit applications
• Supports 40-bit addressing
• provides up to 1 Terabyte of direct memory addressability
• data bus ECC protection
  • Single-bit error correction with double-bit error detection

On Die Cache

• Keeps more needed data closer to the cores for access faster

than off-chip memory

• each CPU core can use the L3 cache without sending a request

back to the system I/O redundantly

• Improves performance by up 60 percent for business

processing (ERP, SCM, CRM)

• Improves 70 percent for transaction processing
• Over twice the performance for e-commerce applications

On Die Cache

On Die Cache

On Die Cache

On Die Cache

Cache Safe Technology

• Improves processor reliability

• Allows processor and server to continue

normal operation in the event of a rare L

cache error; automatically detects and

disables cache lines

• Helps reduce downtime and processor

replacements, improving TCO (Total cost of

ownership)

SpeedStep Technology

• Enhanced Intel SpeedStep Technology
  • Front side bus is not altered; only the internal core frequency is changed
  • Voltage/frequency selection is software controlled by writing to processor Model Specific Registers - If the target frequency is higher than the current frequency, VCC is incremented in steps (+12.5 mV) by placing a new value on the VID signals and the processor shifts to the new frequency - If the target frequency is lower than the current frequency, the processor shifts to the new frequency and VCC is then decremented in steps (-12.5 mV) by changing the target VID through the VID signals

Hyper Pipelined Technology

• 20 stage pipeline
• Drawback of having more stages in a pipeline is an

increase in the number of stages that need to be

traced back in the event that the branch predictor

makes a mistake, increasing the penalty paid for a

misprediction

• To address this issue, Intel devised the Rapid

Execution Engine