Download History of Intel and IBM Microprocessors: Pentium to PowerPC G5 and Core i7 and more Exercises Computer Architecture and Organization in PDF only on Docsity!
Intel Corporation, the world's largest semiconductor chip maker was founded on July
18, 1968 and it is the inventor of the x86 series of microprocessors. Started it’s
“Pentium” series in 1993.
Intel Pentium
Introduced: 1993 Architecture: x Pipeline Stages: 5 Clock Speed: 60-200 MHz Bus Speed: 50, 60 or 66 MHz L2 cache Memory: 256KB to 1MB Transistors Contained: 3.1 to 3.3 million
Intel Pentium II
Introduced: 1997 Architecture: x Pipeline Stages: 14 Clock Speed: 200 - 450 MHz Bus Speed: 66 or 100 MHz L2 cache Memory: 256KB to 512KB Transistors Contained: 7.5 million
Intel Pentium III
Introduced: 1999 Pipeline Stages: 10 Architecture: x Clock Speed: 450 MHz-1.13 GHz Bus Speed: 100 or 133 MHz L2 cache Memory: 256KB to 512KB Transistors Contained: 9.5 to 28 million transistors
Intel Pentium IV
Introduced: 2000 Architecture: x86- Pipeline Stages: 14 Clock Speed: 1.3-3.4 GHz Bus Speed: 400MHZ or 800MHZ L2 cache Memory: 256KB to 2MB Transistors Contained: 42 million transistors
Intel Core i7 (Latest)
Introduced: 2008 Architecture: x86-64bit Pipeline Stages: 16 No of Cores: 8 processing threads Clock Speed: 3.06 GHz, 2.93 GHz, and 2.66 GHz core speed Bus Speed: 1066 MHz L3 cache Memory: 8MB
IBM PowerPC 604/604e
Introduced: 1994 Architecture: 32bit L1 cache Memory: 256KB to 1MB Pipeline Stages: 4 Clock Speed: 166-350MHz Bus Speed: 66 MHz. Transistors Contained: 3.6 to 5.1 million
IBM PowerPC 740/750 (G3)
Introduced: 1997 Architecture: 32bit L1 cache Memory: 256KB to 1MB Clock Speed: 200-366MHz Bus Speed: 66 MHz Transistors Contained: 6.35 million
IBM PowerPC G
Introduced: 1999 Architecture: 32bit L1 cache Memory: 256KB to 1MB Pipeline Stages: 4 Clock Speed: 500MHz Bus Speed: 1066 MHz Transistors Contained: 10.5 million
IBM PowerPC G
Introduced: 2003 Architecture: 64bit L1 cache Memory: 512KB Pipeline Stages: 16 Clock Speed: 2.5GHz Bus Speed: 1066 MHz Transistors Contained: 58 million
IBM Power7 (Latest)
Introduced: February 2010 Architecture: x86-64bit L2 cache Memory: 256 kB L3 cache Memory: 32 MB Pipeline Stages: 12 Clock Speed: 4.04 GHz No of Cores: 4, 6 or 8 cores per chip Bus Speed: 1066 MHz DDR Transistors Contained: 1.2 billion transistors
