Introduction - Multimedia Signal Processing - Lecture Slides, Slides of Electronics engineering

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Introduction

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Objective

• FFT Introduction

• Some FFT algorithms

• FFT on PDSP

• FFT floating to fixed-point conversion

• Hardware implementation of FFT

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FFT Fixed point - Xilinx

• Performing the calculations with no scaling and carrying computation
  • The growth of the fractional bits created from the multiplication are truncated after the multiplication.
  • The width of the output will be the (input width + number of stages + 1).
  • For example, a 1024-pt transform with an input of 16 bits consisting of 1 integer bit and 15 fractional bits, will have an output of 27 bits with 12 integer bits and 15 fractional bits.
• Scaling at each stage using a fixed-scaling schedule
• Scaling automatically using block-floating point

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Block-floating point

– The computation is fixed-point

– After every addition there is an overflow test

– If the overflow is detected the array is divided by

– The number of division is counted to determine

the scale factor

– SNR depends on how many overflows occurs

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Butterfly with Scaling multipliers

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Pipelined FFT-Xilinx core

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Pipelined FFT architecture

- Radix-2 multipath delay commutator (R2MDC) - Radix-2 single-path delay feedback (R2SDC) - Radix-4 multipath delay commutator (R4MDC) - Radix-4 single-path delay commutator (R4SDC) - Radix-4 single-path delay feedback (R4SDF) - Radix-22 single-path delay commutator (R22SDC)

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Radix-2 single-path delay feedback

• The total number of delay elements is N – 1= N/ 2 + N/ 4 +... + 1

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FFT processor

• Datapath
  • memories,
  • butterflies and
  • complex multipliers.
• Control unit

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Resource analysis

• Computation time for the 1024-point FFT
• The number of butterfly operations for Radix
• Assume 1 clock cycle per Butterfly
• The minimum number of Butterflies is
• This is optimal with the assumption that ALL data are available to ALL stages, which is

impossible for continuous data streams. Each butterfly has to be idle for 50% in order to reorder the incoming data.

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Resource analysis

• The solution: the number of butterflies is 10

• The number of complex multipliers is 9

• Memory length for Radix-2 single-path delay

feedback is N-

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Complex multiplier

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Radix - 4

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