Iterative Integer - CAD Based Logic Design - Lecture Slides, Slides of Computer Science

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Iterative Integer Division

Techniques

Division – Basics

• Radix r division is essentially a trial-and-error process, in which the

next quotient bit is chosen from 0, …, r-

353 = D

V = 4

088 = Q

001 = R

• Binary division is much simpler, since the next quotient bit is either a 0

or 1 depending on whether the partial remainder is less than or greater

than/equal to the divisor, respectively

• Integer division: Given 2 integers D the dividend and V the divisor, we

want to obtain an integer quotient Q and an integer remainder R, s.t.

D = V.Q + R, R < V

• Integer–FP division: Given 2 integers D the dividend and V the divisor, we

want to obtain a floating-point (FP) or real quotient s.t.

D ~ V.Q

• SHR-Divisor Method: Start

subtraction of V from left most

position of D; SHR V for next

subtraction every iteration

Division – Handling V with leading 0’s

• Some higher order bits of an n-bit V are 0’s
• One of the main requisites of correct division by repeated subtraction is that the

portion of D (in general the partial remainder) from which V is being subtracted be <

2.V, since the Q bit can only be 0 or 1

• Note that V is stored as a 6-bit # (000100) in the computer. The type of manual

adjustment done in the above example of converting 6-bit subtractions into 4-bit ones

(in general, n-bit subtractions into k-bit ones, k < n) is not possible in a computer

(though a complex circuit may be designable to do variable-bit division)

• Method 1: Shift V to the left by k bits (until its MSB=1), and perform the div. for k+

step (equivalently D is considered a n+k bit #)

011101000 = D

V = 100000

0111 = Q

001000 = R

SHL:

SHL:

SHL: 0101000

Division – Handling V with leading 0’s

• Method 2: Augment D to the left by n-1 0’s, making D a (2n-1)-bit #, while V remains

an n-bit #. Perform the division for n iterations

• Note that this ensures that at least in iteration 1:

the MS n bits of D < 2V. It can be proved that this will be true at the beginning of every

iteration, i.e., after subtraction and SHL of the previous iteration

00000011101 = D

V = 000100

000111 = Q

SHL:

SHL:

SHL:

SHL:

SHL:

000001 = R

• This is the type of division algorithm

used in a computer/digital-hardware

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