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Computer Organization & Architeture

Vinish Kumar

KCS 302

UNIT- I

RAJ KUMAR GOEL INSTITUTE OF TECHNOLOGY,

GHAZIABAD

Organization & Architecture Architecture: Computer Architecture refers to those attributes of a system visible to a programmer or, put another way, those attributes that have direct impact on the logical execution of a program. Examples include the instruction set, the number of bits used to represent various data types (e.g., number, character), I/O mechanisms and techniques for addressing memory. Organization: Computer Organization refers to the operational units and their Interconnections that realize the architectural specifications Examples include those hardware details transparent to the programmer, such as control signals, interfaces between the computer and peripherals and memory technology used.

INTRODUCTION

BUS AND MEMORY TRANSFER BUS : A shared communication path consisting of one or more connections lines is known as bus and the transfer of data through this bus is known as bus transfer. Memory Transfer: When a data is read from the memory or is stored in memory is referred to as memory transfer. Def. : A bidirectional bus used to carry data between two units is data bus. Def. : A unidirectional bus used to carry memory addresses is called memory bus. Def. : The way in which different bus are connected to form common bus, so that CPU, memory and I/O devices can used common bus(Using multiplexer) when required is called bus organization. For a general Bus organization System:- In general a bus system will multiplex K registers of N bits each. No of Multiplexers =N Size of multiplexers =K × 1. No of selection Lines =m ( 2^m)=K Size of decoder will be m× K. Example : Construct a common bus of 4 registers of 4 bits. No of Multiplexers = Size of multiplexers =4 × 1. No of selection Lines =2( 2^2 =4(size of Multiplexer) Size of decoder will be 2× 4.

BUS AND MEMORY TRANSFER

TRANSFER FROM BUS TO A DESTINATION REGISTER

Three-State Bus Buffers Bus line with three-state buffers Reg. R0 Reg. R1 Reg. R2 Reg. R Bus lines 2 x 4 Decoder Load D 0 D 1 D 2 D 3 z w Select E (enable) Output Y=A if C= High-impedence if C= Normal input A Control input C Select Enable 0 1 2 3 S S A B C D Bus line for bit 0

BUS AND MEMORY TRANSFER

BUS ARBITRATION Centralized bus arbitration i) Daisy Chaining method – It is a simple and cheaper method where all the bus masters use the same line for making bus requests. The bus grant signal serially propagates through each master until it encounters the first one that is requesting access to the bus. This master blocks the propagation of the bus grant signal, therefore any other requesting module will not receive the grant signal and hence cannot access the bus. During any bus cycle, the bus master may be any device – the processor or any DMA controller unit, connected to the bus.

BUS ARBITRATION Advantages – a) Simple design b) Less no. of control lines. Disadvantages – a) Priority depends on the physical location of master. b) Propagation delay due to serially granting of bus. c) Failure of one of the devices may fail entire system.

BUS ARBITRATION Advantage: a) Priority flexible. b) One module fails, entire system does not fail. Disadvantage: a) Adding bus masters is different as increases the number of address lines of the circuit.

BUS ARBITRATION (iii) Fixed priority or Independent Request method All bus masters have their individual bus request and bus grant lines. The controller thus knows which master has requested, so bus is granted t that master. Priorities of the masters are predefined so on simultaneous bus requests, the bus is granted based on the priority, provided the bus busy line is not active. The controller consists of encoder and decoder logic for priorities

BUS ARBITRATION Distributed bus arbitration – All devices participating in the selection of the next bus master Here, all the devices participate in the selection of the next bus master. Each device on the bus is assigned a bit identification number. When one or more devices request a control of the bus, they assert the start arbitration signal and place their 4-bit identification numbers on arbitration lines through ARB3.Each device compares the code and changes its bit position accordingly. It does so by placing a 0 at the input of their drive. The distributed arbitration is highly reliable because the bus operations are not dependant on devices.

BUS ARBITRATION

• (^) What is the difference between centralized processing and distributed processing?
• (^) In centralized computing all the processing is handled by a central system. It is more secure as all the data and processing is handled at single place. But if the central system is down the whole system crashes.
• (^) In distributed computing a problem is divided into many tasks and these task are completed by different systems connected through each other over the network. It is less secure than centralized computing as data is distributed across several computers. But even if one or two computer goes down the entire system does not crash. The other computers continue their work. So you can upgrade your system without completely shutting it down.

GENERAL REGISTERS ORGANIZATION

MAJOR COMPONENTS OF CPU

• (^) Storage Components Registers Flags
• (^) Execution (Processing) Components Arithmetic Logic Unit(ALU) Arithmetic calculations, Logical computations, Shifts/Rotates
• (^) Transfer Components Bus
• (^) Control Components Control Unit In Basic Computer, there is only one general purpose register, the Accumulator (AC) In modern CPUs, there are many general purpose registers It is advantageous to have many registers Transfer between registers within the processor are relatively fast Going “off the processor” to access memory is much slower Register File ALU Control Unit

SELA { MUX MUX } SELB

OPR ALU R R R R R R R Input 3 x 8 decoder SELD Load (7 lines) Output A bus B bus Clock GENERAL REGISTERS ORGANIZATION OPERATION OF CONTROL UNIT The control unit Directs the information flow through ALU by

• Selecting various Components in the system
• Selecting the Function of ALU