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Department of Electrical Engineering
Faculty Member:____________________ Dated: ________________ Semester:__________________________ Section: ________________
EE-221: Digital Logic Design
Lab 5: Binary to Gray and Gray to Binary Code Conversion
PLO4/CLO4 PLO4/CLO4 PLO5/CLO5 PLO8/CLO6 PLO9/CLO Name Reg. No Viva / Lab Performanc e Analysis of data in Lab Report Modern Tool Usage Ethics and Safety Individual and Team Work Total marks Obtained 5 Marks 5 Marks 5 Marks 5 Marks 5 Marks 25 Marks Group No.:
Lab5: Part (a): Binary to Gray and Gray to Binary Code Conversion
Lab5: Part (b): Gate-level Modeling in Verilog
Lab Instructions This lab activity comprises three parts, namely Pre-lab, Lab tasks, and Post-Lab Viva session. The lab report will be uploaded on LMS three days before scheduled lab date. The students will get hard copy of lab report, complete the Pre-lab task before coming to the lab and deposit it with teacher/lab engineer for necessary evaluation. Alternately each group to upload completed lab report on LMS for grading. The students will start lab task and demonstrate design steps separately for step-wise evaluation( course instructor/lab engineer will sign each step after ascertaining functional verification) Remember that a neat logic diagram with pins numbered coupled with nicely patched circuit will simplify trouble-shooting process. After the lab, students are expected to unwire the circuit and deposit back components before leaving. The students will complete lab task and submit complete report to Lab Engineer before leaving lab. The Total duration for the lab is 3 hrs. After lab duration, a deduction of 5 marks per day will be done for late submission. A lab with in-complete lab tasks will not be accepted. There are related questions at the end of this activity. Give complete answers.
W=
X=
Y=
Z=
HINT: Our inputs and outputs are of 4-bit each. You will have to make 4 K-Maps (Consider W as independent function of A,B,C,D, Make K-Map and simplify it). Arrive at the simplest expression for each output. Dec Binary Gray A B C D W X Y Z
A=
B=
C=
D=
HINT: Our inputs and outputs are of 4-bit each. You will have to make 4 K-Maps (Consider A as independent function of W,X,Y,Z. Make K- Map and simplify it). Arrive at the simplest expression for each output. Dec Gray Binary W X Y Z A B C D
Lab Tasks: (To be completed in the lab) (3 marks)
Lab Task 1: Implement the Binary to Gray Code Converter using Basic gates (AND, OR, NOT). Make the Schematic Diagram. Show the results to your Teacher/Lab Engr. What and how many gates did you use? Do not dispatch your hardware. You will need it in lab task 3.
Lab Task 2: Realize the Gray to Binary Code Converter using exclusive-OR gates. Make the Schematic Diagram. Show the results to your Teacher/ Lab Engr. What and how many gates did you use? Do not dispatch your hardware. You will need it in lab task 3.
Lab Task 4: Design and simulate the gate-level model of the circuit you patched in task 3. Give the code in the space provided below.
