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Lab 3: Digital Logic Design Page 1
Department of Electrical Engineering
FacultyMember: Date 30,MARCH,
Course/Section:DLD Semester:4TH
EE-241: Digital Logic Design
Lab4: Part (a): Binary to Gray Code Conversion
Lab4: Part (b): Gate-level Modeling in Verilog
Lab4: Part (a): Binary to Gray Code Conversion
Name Reg. No. Report
Marks /
Viva
Marks /
Total/
SALMAN TARIQ
MUHAMMAD ABDULLAH 062
FARJAD ABID 073
This Lab has been divided into two parts.
In first part you are required to design and implement a binary to gray and gray to binary code
converter. You will be cascading these two converters thus implementing a binary to gray coderdocsity.com
Lab 3: Digital Logic Design Page 2
Pre-Lab Tasks: (To be done before coming to the lab)
What do you mean by binary codes for the decimal digits? Give some examples and codes (tables) for the decimal digits. ๏ท An n bit binary code is a group of n bits that assumes up to distinct combinations of 1โs and 0โs with each combination representing one element of the set that is being coded. (1 Mark) ๏ท Binary codes are a way to represent information in binary numbers. ๏ท By using binary codes we can present decimal numbers in computer understandable form.
Examples are
๏ Access-3 code ๏ Binary coded decimal codes ๏ Gray codes ๏ 8 4 -2 -
Lab 3: Digital Logic Design Page 4
- In the lab you would be implementing a gray to binary and binary to gray code converter. Make a truth table for both the codes by filling in the following tables and Simplify the expressions for W,X,Y,Z in terms of A,B,C,D and vice versa.( Use backside of the page if necessary). Also give some applications in which gray code could be used. (4 Marks)
W=A
X=AโB + ABโ=A โ B
Y=BโC + BCโ=B โ C
Z=CโD + CDโ=C โ D
Decimal Binary Gray
--------- A B C D W X Y Z
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
2 0 0 1 0 0 0 1 1
3 0 0 1 1 0 1 1 0
4 0 1 0 0 0 1 1 0
5 0 1 0 1 0 1 1 1
6 0 1 1 0 0 1 0 1
7 0 1 1 1 0 1 0 0
8 1 0 0 0 1 1 0 0
9 1 0 0 1 1 1 0 1
10 1 0 1 0 1 1 1 1
11 1 0 1 1 1 1 1 0
12 1 1 0 0 1 0 1 0
13 1 1 0 1 1 0 1 1
14 1 1 1 0 1 0 0 1
15 1 1 1 0 1 0 0 0
HINT:
Our inputs and outputs are of 4-bit each. You will have to make 4 K-Maps (Consider W as independent function of A,B,C,D, Make K-Map and simplify it). Arrive at the simplest expression for each output.
Lab 3: Digital Logic Design Page 5
A=W
B=W โ X
C=W โ X โ Y
D=W โXโYโZ
- Draw the logic diagram for the above codes in the space provided below. (2 Marks)
Decimal Gray Binary
--------- W^ X^ Y^ Z^ A^ B^ C^ D 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 2 0 0 1 1 0 0 1 0 3 0 1 1 0 0 0 1 1 4 0 1 1 0 0 1 0 0 5 0 1 1 1 0 1 0 1 6 0 1 0 1 0 1 1 0 7 0 1 0 0 0 1 1 1 8 1 1 0 0 1 0 0 0 9 1 1 0 1 1 0 0 1 10 1 1 1 1 1 0 1 0 11 1 1 1 0 1 0 1 1 12 1 0 1 0 1 1 0 0 13 1 0 1 1 1 1 0 1 14 1 0 0 1 1 1 1 0 15 1 0 0 0 1 1 1 0
W
X
Y
Z
A
B
C
D
A
B
C
D
HINT:
Our inputs and outputs are of 4-bit each. You will have to make 4 K-Maps (Consider A as independent function of W,X,Y,Z. Make K-Map and simplify it). Arrive at the simplest expression for each output.
Binary
Gray
Binary
Lab 3: Digital Logic Design Page 7
Implement the Gray to Binary Code Converter. Make the Schematic Diagram. Show the results to your Lab Instructor / Assistant. What and how many gates did you use? Donot dispatch your hardware.You will need it in lab task 3. (3 Marks)
We have used 4 XOR(one XOR was used for buffer)
A=W โ 0
B=W โ X
C=W โ X โ Y
D=W โXโYโZ
We can also implement the same circuit by 3 gates(if we do not use
buffer).But by using buffer number of fan-outs in the circuit is
increased.
Lab Task 3:
Now cascade the two circuits in series by connecting the outputs of binary to gray converter to the inputs of the gray to binary converter. You should be able to get the binary input at output as well. Show the results to your Lab Instructor / Assistant. (6 Marks)
Lab5: Part (b): Gate-level Modeling in Verilog
Lab Task4:
Design and simulate the gate-level model of the circuit you patched. Give the code in the space provided below.
Code of Binary to Grey. (5 marks)
module btg (w,x,y,z,a,b,c,d);
output w,x,y,z;
input a,b,c,d;
xor x1(w,a,0);
xor x2(x,a,b);
xor x3(y,b,c);
Lab 3: Digital Logic Design Page 8
xor x4(z,c,d);
endmodule
Time-Line Diagram of Binary to Grey Code.
Code of Grey to Binary.
module gtb(a,b,c,d,w,x,y,z);
output a,b,c,d;
input w,x,y,z;
xor xr1(a,w,0);
xor xr2(b,w,x);
xor xr3(c,w,x,y);
xor xr4(d,w,x,y,z);
endmodule
Time-Line Diagram of Grey Code to Binary.
Lab 3: Digital Logic Design Page 10
The lab marks will be condensed to 12.5 Marks.
