LC3b Interrupt and Exception Handling: State Diagram, Datapath, and Microsequencer, Study Guides, Projects, Research of Computer Programming

Download LC3b Interrupt and Exception Handling: State Diagram, Datapath, and Microsequencer and more Study Guides, Projects, Research Computer Programming in PDF only on Docsity!

Readme document describing the new states, Datapath, control signals,

and microsequencer for the lc3b. SG

General Overview of how the interrupt states fit into the current state diagram

Figure 1 : How the interrupt and exception states fit into the overall state diagram

State-by-State description

Modified States: State 18: Like the non-modified state diagram except we change to state 41 if the IE bit is set. State 3 3 : Like the non-modified state diagram except we change to state 63 or state 62 based on the exception set. State 29 & 17 : Like the non-modified state diagram except we change to state 63 if the protection exception is set. State 25 & 16 : Like the non-modified state diagram except we change to state 63 or state 62 based on the exception set. Interrupt & Exception specific States: State 10 & 11: If we are in either of these two states, that means an unknown opcode has been inputted.

1. Load the vector register with: concat(0x02, LSHF(0x0 4 )).
2. Load the MDR with the PSR.
3. Go to State 42. State 62 : If we are in this state, that means the MAR was unaligned in a memory operation.
4. Load the vector register with: concat(0x02, LSHF(0x0 3 )).
5. Load the MDR with the PSR.
6. Go to State 42. State 63 : If we are in this state, that means we were accessing protected memory.
7. Load the vector register with: concat(0x02, LSHF(0x0 2 )).
8. Load the MDR with the PSR.
9. Go to State 42. State 41: If we are in this state, that means we are taking an interrupt.
10. Load the vector register with: concat(0x02, LSHF(0x0 1 )).
11. Load the MDR with the PSR.
12. Clear the Interrupt Flag.
13. Go to State 42. State 42:
14. Set the new PSR privilege bit to supervisor mode.
15. Check the current PSR privilege bit to see what the next state is.
16. Go to State 50 or 34.

State 50: If we are in this state, that means we have just exited user mode.

1. Save the user stack pointer (USP) into the register “Saved_USP.”
2. Load the initialized supervisor stack pointer (SSP) into R6.
3. Go to State 34. State 34:
4. Load the decremented SSP into R6.
5. Load the decremented SSP into MAR.
6. Go to State 37. State 37: A simple memory operation that loads the PSR into the memory specified by the decremented SSP. State 3 9 : Same as State 34. State 38:
7. Load the PC – 2 into the MDR.
8. Go to State 44. State 44: A simple memory operation that loads PC – 2 into the memory specified by the decremented SSP. State 46:
9. Load the address of the trap table that holds the corresponding routine
10. Go to State 45. State 45: A simple memory operation that grabs the PC value from the memory location specified by the Vector register. State 47:
11. Load the PC from the MDR
12. Start the routine (i.e. go to state 18)

State-by-State description

New States: State 8:

1. Load the incremented SSP into R6.
2. Load the SSP into the MAR.
3. Go to State 49. State 49: A simple memory operation that grabs the PC off the stack. State 51:
4. Load the saved PC into the PC register.
5. Go to State 40. State 40: Same as State 8. State 52: A simple memory operation that grabs the PSR off the stack. State 54:
6. Load the saved PSR into the PSR.
7. Go to State 55. State 55: Depending on the loaded privilege bit, go to State 43 or State 59. State 43: Do nothing. Go to State 18. State 59:
8. Restore the R6 with the USP.
9. Go to State 18.

Modified Datapath

Figure 4 : Modified Datapath

Figure 7 : Select whether to load the bus, R6+2, or SSP into the corresponding register based on the control signal

REGISTERMUX.

Figure 8 : When LD.USP is high, the USP is saved into Saved_USP. SPMUX sends either the incremented SSP, decremented SSP,

or the Saved_USP onto the bus.

Figure 9 : GatePSR pushes the PSR onto the bus. LD.PV, LD.PRI, and LD.PSR load the old PSR or new values set by the muxes.

PVMUX selects between supervisor state and the popped PSR[15]. PRIMUX selects between a priority of 1 (highest) and the

popped PSR[14]. CCMUX selects between the NZP logic block and the popped PSR[2:0]. AS you can see in the image above,

the additional microsequencer signals are shown (PSR[15], UN, P, IE).

Modified microinstructions

• 000000 (state 0) IRD LD.MAR LD.MDR LD.IR LD.BEN LD.REG LD.CC LD.PC GatePC GateMDR GateALU GateMARMUX GateSHF DRMUX SR1MUX ADDR1MUX MARMUX MIO.EN R.W DATA.SIZE LSHF1 CLEAR.INT Cond3 LD.VECTOR LD.PV LD.PSR LD.SAVED_USP LD.PRI GateVector GatePC1 GatePSR GateSP PVMUX CCMUX DRMUX2 SRMUX2 PRIMUX
• 000001 (state 1)
• 000010 (state 2)
• 000011 (state 3)
• 000100 (state 4)
• 000101 (state 5)
• 000110 (state 6)
• 000111 (state 7)
• 001000 (state 8)
• 001001 (state 9)
• 001010 (state 10)
• 001011 (state 11)
• 001100 (state 12)
• 001101 (state 13)
• 001110 (state 14)
• 001111 (state 15)
• 010000 (state 16)
• 010001 (state 17)
• 010010 (state 18)
• 010011 (state 19)
• 010100 (state 20)
• 010101 (state 21)
• 010110 (state 22)
• 010111 (state 23)
• 011000 (state 24)
• 011001 (state 25)
• 011010 (state 26)
• 011011 (state 27)
• 011100 (state 28)
• 011101 (state 29)
• 011110 (state 30)
• 011111 (state 31)
• 100000 (state 32)
• 100001 (state 33)
• 100010 (state 34)
• 100011 (state 35)
• 100100 (state 36)
• 100101 (state 37)
• 100110 (state 38)
• 100111 (state 39)
• 101000 (state 40)
• 101001 (state 41)
• 101010 (state 42)
• 101011 (state 43)
• 101100 (state 44)
• 101101 (state 45)
• 101110 (state 46)
• 101111 (state 47)
• 110000 (state 48)
• 110001 (state 49)
• 110010 (state 50)
• 110011 (state 51)
• 110100 (state 52)
• 110101 (state 53)
• 110110 (state 54)
• 110111 (state 55)
• 111000 (state 56)
• 111001 (state 57)
• 111010 (state 58)
• 111011 (state 59)
• 111100 (state 60)
• 111101 (state 61)
• 111110 (state 62)
• 111111 (state 63)