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TKK “Laitteistokuvauskielinen digitaalisuunnitelu” Syksy-

VERILOG

TKK “Laitteistokuvauskielinen digitaalisuunnitelu” Syksy-

History

• Developed by Gateway Design Automation
• Bought by Cadence Design Systems
• Now an IEEE standard : IEEE-
• Pure language definition
• Website of links see www.esperan.com

TKK “Laitteistokuvauskielinen digitaalisuunnitelu” Syksy-

Instantiation

• Like VHDL named and inffered port mapping allowed.
• Unlike VHDL no configuration file is supported. However, order of compilation is not important. module FULLADD( A, B, CIN, SUM, CARRY); input A, B, CIN; output SUM, CARRY;

wire N_SUM, CARRY1, CARRY2;

HALFADD u1(A, B, N_SUM, CARRY1); HALFADD u2(.B(N_SUM), .A(CIN), .SUM(SUM), .CARRY(CARRY2)); or u3(CARRY, CARRY2, CARRY1);

endmodule

Similar to a signal definition

The or is a built in gate primitive within Verilog

TKK “Laitteistokuvauskielinen digitaalisuunnitelu” Syksy-

Sequential Statements

• In VHDL one has the PROCESS statement. In VERILOG on has the ALWAYS and INITIAL statements. module ZOR(A, B, Z_OR); input A,B; output Z_OR; reg Z_OR;

always @(A or B) begin if ((A == 1) | (b == 1)) Z_OR <= 1; else Z_OR <= 0; end endmodule

If output is generated in a sequential statement block it must be of a register type.

Sensitivity list.

All sequential statements are enclosed by a begin and an end (unless there is only one statement in the branch)

TKK “Laitteistokuvauskielinen digitaalisuunnitelu” Syksy-

Data Types

• Verilog objects communicate using variables (this is only a different name as from VHDL)
• All variables have a type
• Verilog has built in types (i.e. enumerated types are not supported)
• There are two classes of data types
  • Register
  • Net
• The type must be defined when the variable is declared.
• Module ports are wire by default. Need to be redefined in certain conditions.

TKK “Laitteistokuvauskielinen digitaalisuunnitelu” Syksy-

Net Data Types

• Unlike VHDL resolution functions are built in to the net definitions
• List of some net types
  • wire
  • tri
  • wand (Wired AND so a resolved type)
  • wor (Wired OR)
• Possible values
  • 1'b1, 1'b0, 1'bx, 1'bz
  • 4'b

1 is the width of the bus ' is the base indicator b is binary z is value

TKK “Laitteistokuvauskielinen digitaalisuunnitelu” Syksy-

Vectors

• Example of vector definition. Bit order is defined when the vector is declared. - reg [3:0] UP_BUS; - wire [15:4];
• Vector assignment
  • Vector to vector. Elements are assigned by position not element number. Therefore, remember to number in a consistent manner.
  • Vector values can be decimal (default), hexadecimal, octal or binary
    • bus <= 8'o67 (Note that the leading elements, if any, are stuffed to zero)

TKK “Laitteistokuvauskielinen digitaalisuunnitelu” Syksy-

Arrays

• Verilog support for more complex data structures is limited. Only two dimensional arrays are supported. Records and larger arrays are nor supported.
• Definition of array
  • reg [7:0] MEM[255:0] This gives a 8 bit wide 256 locations deep array
  • integer NUM[99:0] An integer is already a vector.

TKK “Laitteistokuvauskielinen digitaalisuunnitelu” Syksy-

Operators

• Verilog has a full set of operators. (Rather C type that VHDL)
• Arithmetic operators
  • • Add, - Subtract, * Multiply, / Divide, % Modulus
• Bit-wise operators. Normally used on vectors. Each element considered sperately - ~ Not, & And, | or, ^ xor, ~^ xnor
• Logical operators. Return a 1, 0 or X -! Not, && And, || Or
• Relational and Equalities

  • greater than, < less than, >= greater than or equal, == logical equality

• Other more "esoteric" operators exist.

TKK “Laitteistokuvauskielinen digitaalisuunnitelu” Syksy-

Conditional statements

• The IF and CASE statements are supported
• IF if (CONDITION) begin // sequential statements end else if (CONDITION) begin // sequential statements end else begin // sequential statements end

TKK “Laitteistokuvauskielinen digitaalisuunnitelu” Syksy-

FOR LOOP

• Unlike VHDL the loop variable must be declared

integer I; . . for (I = 0; I < 4; I = I + 1) begin Z <= I; end

TKK “Laitteistokuvauskielinen digitaalisuunnitelu” Syksy-

Repeat and While loops

• WHILE

while ($time < 800) begin @(negedge CLK); A <= B; end

• REPEAT repeat (12) begin @(posedge CLK); A <= B; end

TKK “Laitteistokuvauskielinen digitaalisuunnitelu” Syksy-

Function

function integer COUNT; input [7:0] IN_BUS; integer I; begin COUNT = 0; for ( I= 0; I < 8; I = I + 1) if (! IN_BUS[I]) COUNT = COUNT + 1; end endfunction

Function calls: wire [2:0] COUNT_B = COUNT(BUS); if (COUNT(BUS) == 0 )

Return type. Default is reg

Function name

Function name is the return value name

TKK “Laitteistokuvauskielinen digitaalisuunnitelu” Syksy-

Task

task CLOCK; input [31:0] NUMBER; begin repeat (NUMBER) @(negedge CLK); end endtask

TASK calls CLOCK (counter)

Visible from the calling function