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CORK INSTITUTE OF TECHNOLOGY
INSTITIÚID TEICNEOLAÍOCHTA CHORCAÍ
Autumn Examinations 2008/
Module Title: Digital Systems 2
Module Code: ELTR
School: Electrical and Electronic Engineering
Programme Title: Bachelor of Engineering in Electronic Engineering – Stage 1
Programme Code: EELXE_7_Y
External Examiner(s): Mr D Denieffe Dr P O’Sullivan
Internal Examiner(s): Mr J O’Sullivan
Instructions: Attempt any three questions. All questions carry equal marks. Ensure to include the Return Sheet with your answer book.
Duration: Two hours
Sitting: Autumn 2009
Requirements for this examination: N/A
Note to Candidates: Please check the Programme Title and the Module Title to ensure that you have received the correct examination paper. If in doubt please contact an Invigilator.
You are expected to present your material in a neat and clear fashion. Start each question on a new page. Remember that you have plenty of time for this exam – two hours for three questions.
Q1 (a) With respect to flip-flops, explain the difference between synchronous and asynchronous inputs. [2 marks]
(b) Draw a logic symbol and truth table for an S-R flip-flop with synchronous and asynchronous inputs. State which of the inputs are synchronous and which are asynchronous. [5 marks]
(c) Draw a full logic diagram of the flip-flop circuit in (b) above. [5 marks]
(d) Figure 1 below shows the diagram of a logic circuit that we covered during the course but drawn in a slightly different configuration to that in our notes. Identify this circuit and indicate where it might be used. [2 marks]
(e) Describe fully the action of the circuit in Figure 1 and the function of all input and output lines shown. [6 marks]
CLR
D Q
CLR
D Q
CLR
D Q
CLR
D Q
A B C D
W X Y^ Z
P Q
Figure 1
Q2 (a) With the aid of simple block diagrams, identify the three main types of shift register circuits. [6 marks]
(b) Draw a full logic diagram of one of the shift register circuits in (a). [4 marks]
(c) Accompanying this paper is an extract from the data sheet for the 74LS shift register, © Fairchild Semiconductor. Study the sheet and give brief answers to the following questions: (i) How is data loaded in parallel into this device? (ii) How can the clock signal be inhibited in this device? (iii) What is the largest voltage that can safely be applied to this device? (iv) What is the minimum duration of load pulse for this device? [4 marks]
(d) Using a functional block diagram, show how a 16-bit shift register with a parallel-load facility can be wired up using 74LS165 chips. [6 marks]
Q4 (a) In relation to combinational logic circuits, briefly explain what is meant by a magnitude comparator. [2 marks]
(b) With the aid of truth tables, Boolean equations and circuit diagrams, design simple logic circuits to provide the following magnitude comparator functions for two single-bit inputs, A and B in each case: (i) A > B (ii) A = B (iii) A < B [9 marks]
(c) State what inputs and outputs you would expect to find on a 4-bit magnitude comparator chip. [3 marks] (d) Figure 3 below shows the logic symbol for a 2-bit binary decoder with active- LOW outputs and an active-LOW enable input. Draw up a truth table for this decoder and use it to complete the timing diagram on the Return Sheet attached to this paper [6 marks]
A
A
Y
Y
Y
Y
EN
Figure 3
CORK INSTITUTE OF TECHNOLOGY
INSTITIÚID TEICNEOLAÍOCHTA CHORCAÍ
Semester 2 Examinations 2008/
Module Title: Digital Systems 2
Return Sheet
A
A
EN
Y
Y
Y
Y
Name: Return this sheet with your answer book
