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CORK INSTITUTE OF TECHNOLOGY
INSTITIÚID TEICNEOLAÍOCHTA CHORCAÍ
Autumn Examinations 2010
Module Title: Digital Principles
Module Code: ELTR
School: School of Electrical & Electronic Engineering
Programme Title: Bachelor of Engineering in Electronic Engineering
Programme Code: EELXE_7_Y
External Examiner(s): Dr. P. O’Sullivan, Dr. A. Donnellan Internal Examiner(s): Mr. J. O’Driscoll
Instructions: Answer all questions. All questions carry equal marks
Duration: 2 hours
Sitting: Autumn 2010
Requirements for this examination:
Note to Candidates: Please check the Programme Title and the Module Title to ensure that you have received the correct examination paper. If in doubt please contact an Invigilator.
Q1. (a) Figure 1 shows the circuit of a standard TTL 2-input NAND gate. Describe its operation. [10 marks]
Figure 1
(b) With standard TTL logic gates, it is often necessary to connect a 0.01 μF capacitor between the V CC and GND (ground) connections. Briefly explain why this might be necessary. [7 marks]
(c) The 7405 IC contains six INVERTERs with open-collector outputs. If the inverters are connected together in a wired-AND configuration as shown in Figure 1, determine:
(i) the logic expression for the output x , [2 marks] (ii) the minimum preferred value for pull-up resistor RC if output x is to drive other circuits with a total loading factor of 4 U.L. (unit loads). [6 marks]
Q4. (a) Draw a circuit schematic to show how the tri-state buffer may be used to implement a bi-directional data connection. [4 marks] Describe its operation in both ‘read’ and ‘write’ mode. [4 marks]
(b) Compare and contrast static RAM (SRAM) and dynamic RAM (DRAM) memories under the headings: [9 marks]
(i) capacity (ii) speed (iii) cost
(c) Given two 256 × 4-bit ROM memory chips, draw a circuit to show how they should be connected to create a 256 × 8-bit memory system. [8 marks]
