Partial preview of the text
Download Mem3 and more Lecture notes Computer Architecture and Organization in PDF only on Docsity!
— fi wee 484 MEMORY ORGANIZATION cH. 12 bits of ROM than of RAM, because the internal binary cells in ROM occupy less space than in RAM. For this reason. the diagram specifies a 512-byte ROM, while the RAM has only 128 bytes. The 9 address lines in the ROM chip specify any one of the 512 bytes stored in it. The two chip select inputs must be CS} = 1 and CS2 = 0 for the unit to operate. therwise, the data bus is in a hig impedance state. There js no need for a read or write control because the unit can only read, Thus. when the chip is enabled by the two select inputs, the byte selected by the address lines appears on the data bus. Memory Address Map The desi required er of a microcomfputer-system must calculate the amount of memory for the particular appligation and assign it to either RAM or ROM. The interconnection between memory and microprocessor 16 then established from knowledge of the size of memory needed and the type of RAM and ROM chips available. The addressing of memory can be established by means of a table that speci- fies the memory address assigned to eacn chip. The table. called a memory address ma, js 2 pictorial representation of assigned address space for cach chip in the system. To demonstrate with a particul ample, assume that a microcomputer system s 512 bytes of RAM and S12 bytes of ROM. The RAM and ROM chips to be used are specified in Figs. 12-3 and 12-4. The memory address map for this configura- tion is shown in Table 32-1. The component column specifies whether 2 RAM or 4 TABLE 12-1 Memory Address Map for Micronrocomputer Address bus Hexadecimal address 10.9 Tes ak Biel RAM IO. 00000079F' (00 O XXX XARR RAM2t oos0-00FF> JO O Tx xe XX ER RAM 32 — 0100-017F \° 1 OxXXK XXX RAM 43 ol8-OIFF \O 1 1% x x XX ® ROM Q200-03FE yl k ox x xX XX XS ov ROM chip is used. The heaadecimal address column assigns a Tange of hexadecimai equivalent addresses for each chip. The address bus lines are listed in the third column. Although there are 16 lines in the address bus, the table shows only 10 lines because the other 6 are rot used in this example and are assumed to he zero. The small x's under the address bus lincs designate those lines that must be connected to the address inputs in each chip. The RAM chips have J28 byte: d 7 address lines. The ROM chip has 512 bytes and needs 9 address lines. “Vhe x's are always assigned to the lo bus ines: lines 1 through 7 for the RAM and lines 1 through 9 for the ROM. Iti necessary to distinguish between four RAM chips by ass! 
