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Typical system view of the memory hierarchy
Virtual Memory - programmer views memory as large address space without concerns about the amount of physical memory or memory management. (What do the terms 32-bit (or 64-bit) operating system mean?)
Benefits:
- programs can be bigger that physical memory size since only a portion of them may actually be in physical memory
- higher degree of multiprogramming is possible since only portions of programs are in memory
An Operating System goal with hardware support is to make virtual memory efficient and transparent to the user.
Memory-Management Unit (MMU) for paging
CPU
Physical Memory
page 0
page 0 page 3
page 3
page 1
page 1 page 4
page 4
page 2
page 2 page 5
page 5
page 6
page 6
Process A
Process B
Frame Number
page 3 of A
page 5 of B
page 2 of A page 4 of B
page 5 of A
page 2 of B
page 0 of A
page# offset frame# offset 5 50 50
Running Process A (^) Frame#
Valid Bit 0 1 2 3 4 5 6 1 0 1 1 0 1 0 4 - 5 1 - 2 -
Page Table for A
Logical Addr. Physical Addr.
Note: The “Valid” bit is called the Resident R-bit in the textbook (Figure 9.29).
Cache and Virtual Memory - 7
Demand paging is a common way for OSs to implement virtual memory. Demand paging (“lazy pager”) only brings a page into physical memory when it is needed. A “Valid bit” is used in a page table entry to indicate if the page is in memory or only on disk.
A page fault occurs when the CPU generates a logical address for a page that is not in physical memory. The MMU will cause a page-fault trap (interrupt) to the OS.
Steps for OS’s page-fault trap handler:
Check page table to see if the page is valid (exists in logical address space). If it is invalid, terminate the process; otherwise continue.
Find a free frame in physical memory (take one from the free-frame list or replace a page currently in memory).
Schedule a disk read operation to bring the page into the free page frame. (We might first need to schedule a previous disk write operation to update the virtual memory copy of a “dirty” page that we are replacing.)
Since the disk operations are soooooo slooooooow, the OS would context switch to another ready process selected from the ready queue.
After the disk (a DMA device) reads the page into memory, it involves an I/O completion interrupt. The OS will then update the PCB and page table for the process to indicate that the page in now in memory and the process is ready to run.
When the process is selected by the short-term scheduler to run, it repeats the instruction that caused the page fault. The memory reference that caused the page fault will now succeed.
Performance of Demand Paging To achieve acceptable performance degradation (5-10%) of our virtual memory, we must have a very low page fault rate (probability that a page fault will occur on a memory reference).
When does a CPU perform a memory reference?
- Fetch instructions into CPU to be executed
- Fetch operands used in an instruction (load and store instructions on RISC machines)
Example: Let p be the page fault rate, and ma be the memory-access time. Assume that p = 0.02, ma = 50 ns and the time to perform a page fault is 12,200,000 ns (12.2 ms).
effective memory access time
prob. of no page fault
main memory access time
prob. of page fault
page fault time = (1 - p) * 50ns + p * 12,200, = 0.98 * 50ns + 0.02 * 12,200, = 244,049ns The program would appear to run very slowly!!!
If we only want say 10% slow down of our memory, then the page fault rate must be much better!
55 = (1 - p) * 50ns + p * 12,200,000ns
55 = 50 - 50p + 12,200,000p
p = 0.0000004 or 1 page fault in 2,439,990 references
Fortunately, programs exhibit locality of reference that helps achieve low page-fault rates. Page size is typically 4 KB.
Cache and Virtual Memory - 8
Segmentation - divides virtual address space in terms of meaningful program modules which allows each to be associated with different protection. For example, a segment containing a matrix multiplication subprogram could be shared by several programs.
Programmer views memory as multiple address spaces, i.e., segments. Memory references consist of two parts: < segment #, offset within segment >.
As in paging, the
Main (^0 0 00 ) (^1 1 11 )
Subpgm A Subpgm B Global Data Run-time Stack
segment 0
segment 1
segment 2
segment 3
segment 4
operating system with hardware support can move segments into and out of memory as needed by the program.
Each process (running program) has its own segment table similar to a page table for performing address translations.
CPU
Physical
seg.# offset 3 10
Running Process X Location
Valid Bit 0 1 2 3 4 5 6 1 0 0 1 1 1 0 20000
2024
Segment Table for X
Logical Addr. Physical Addr.
Main
Main
seg 0
seg 0
Subpgm
Stack Stack
Global
Global
Subpgm
B
A
seg 2
seg 4
seg 4
seg 3
seg 3
seg 1
Data
Data
Length 101 781 641 1241 10001
Problems with Segmentation:
- hard to manage memory efficiently due to internal fragmentation
- segments can be large in size so not many can be loaded into memory at one time
Solution: Combination of paging with segmentation by paging each segment.
Cache and Virtual Memory - 10
CPU
seg.# offset 3 1034
Running Process X
Valid Bit 0 1 2 3 4 5 6 1 1 1 1 1 0 0
Segment Table for X
Logical Addr.
Physical Memory
Frame Number
page 0 of seg 0
page 4 of seg 4
page 2 of seg 4 page 0 of seg 1
page 0 of seg 3
page 3 of seg 4
page 1 of seg 3
Pointer to Page Table
frame# offset
Frame#
Frame#
Frame#
Frame#
Valid
Valid
Valid
Valid
Bit
Bit
Bit
Bit
Page Table for Seg. 0
Page Table for Seg. 1
Page Table for Seg. 2
Page Table for Seg. 3
Physical Addr.
page offset
Cache and Virtual Memory - 11
