Homework 9: Memory Systems
ECE 2030 A, B (Schimmel) - Solutions
1. True or False: Only Statements (b) and (e) are true. The others are false. Reasons were not
required to be given, and are provided here for explanation only.
a. DRAM incorporates an inverter loop to store one bit of data per cell.
This is true of SRAM, not DRAM.
b. SRAM uses more transistors per bit than DRAM.
True.
c. DRAM is slower than SRAM because it uses flip-flops rather than latches.
DRAM is slower, but the reason has nothing to do with flip-flops.
d. SRAM does not require analog circuitry to read data.
A sense amplifier (analog device) is required to read data.
e. DRAM requires periodic “refreshing” due to capacitor discharge and leakage.
True.
f. SRAM stands for “Static Read Access Memory.”
“Static Random Access Memory”
g. For a given chip size, SRAM contains more bits of memory than DRAM.
DRAM uses fewer transistors, hence can fit more memory per unit area.
2. Fill in the blank with a numeral (expressed in base 10):
a. 10 bytes is equivalent to __20___ nibbles.
b. A memory system with 10 address bits has _1024__ unique addresses.
c. A memory system with 1G (or 230) unique addresses requires __30___ address bits.
3. Design a 1024 x 8 memory system using 1024 x 4 chips.
1024
x
4
A9:0
_
R/W
CS
D3:0
1024
x
4
A9:0
_
R/W
CS
D3:0
10
10
4
4
D7:4
D3:0
A9:0
_
R/W
CS
