R.M. Dansereau; v.1.0
INTRO. TO COMP. ENG.
CHAPTER X-1
MEMORY SYSTEMS
•CHAPTER X
CHAPTER X
MEMORY SYSTEMS
READ MEMORY NOTES ON COURSE WEBPAGE
CONSIDER READING PAGES 285-310 FROM MANO AND KIME
OTHER USEFUL RAM MATERIAL AT ARS TECHNICA
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Memory Systems - Lecture Slides | ECE 2030, Study notes of Electrical and Electronics Engineering
Material Type: Notes; Class: Intro to Computer Engr; Subject: Electrical & Computer Engr; University: Georgia Institute of Technology-Main Campus; Term: Fall 2006;
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INTRO. TO COMP. ENG.
CHAPTER X- MEMORY SYSTEMS
•CHAPTER X
CHAPTER X
MEMORY SYSTEMS
READ MEMORY NOTES ON COURSE WEBPAGE
CONSIDER READING PAGES 285-310 FROM MANO AND KIME
OTHER USEFUL RAM MATERIAL AT ARS TECHNICA
INTRO. TO COMP. ENG.
CHAPTER X-
MEMORY SYSTEMS
INTRODUCTION
MEMORY SYSTEMS
- MEMORY SYSTEMS
-INTRODUCTION
-^
A number of different types of memories and programmable logic devicesexist.•^
Random-access memory (RAM)
-^
Read-only memory (ROM)
-^
Programmable logic devices (PLDs)
•^
Programmable logic arrays (PLAs)
-^
Programmable array logic (PAL)
-^
Programmable gate arrays (PGAs)
•^
Programmable sequential arrays (PSAs)
-^
Field-programmable gate arrays (FPGAs)
-^
Due to time limitations, we will only cover RAM.
Two-level combinational
networks
Multi-level
combinational
Two-level
and sequentialnetworks
Memories
INTRO. TO COMP. ENG.
CHAPTER X-
STATIC RAM^ SRAM CELLS (1)
MEMORY SYSTEMS
- MEMORY SYSTEMS
-INTRODUCTION-TYPES OF RAM
-^
An inefficient SRAM bit cell can be formed as follows.
-^
How many transistors required for this design? •^
24 for inverters + 22 for TGs = 12 transistors.
-^
Select (word line) Very expensive in terms of silicon real estate!!!
D
D
TG
TG
INTRO. TO COMP. ENG.
CHAPTER X-
STATIC RAM^ SRAM CELLS (2)
MEMORY SYSTEMS
- MEMORY SYSTEMS • STATIC RAM
-SRAM CELLS
-^
The structure for a 6 transistor implementation of an SRAM 1-bit cell is asfollows. (We will refer to this as the
6T
”^
design)
•^
The select, or word line, chooses the bit cell when high.
•^
When selected, the new
/^
is latched into the feedback loop.
Select (word line)
D
D
6T design
D D
INTRO. TO COMP. ENG.
CHAPTER X-
STATIC RAM^ SRAM CELLS (4)
MEMORY SYSTEMS
- MEMORY SYSTEMS • STATIC RAM
-SRAM CELLS
-^
A 4 transistor design for an SRAM bit cell is as follows. •^
Notice replacement of pMOS transistors with load resistors.
-^
This is for your own information. We won
’t be testing on the 4T design.
Select (word line)
D
D
4T design
V
DD
INTRO. TO COMP. ENG.
CHAPTER X-
DYNAMIC RAM
DRAM CELLS (1)
MEMORY SYSTEMS
- MEMORY SYSTEMS • STATIC RAM
-SRAM CELLS
-^
A dynamic RAM cell stores the bit as a charge in a capacitor.
-^
This bit must be refreshed periodically (>100s of times a second).
-^
How many transistors required for this design? •^
21 for TG and 21 for inverter = 4 transistors.
-^
Still expensive considering the extra refresh circuitry required!
Select (word line)
D
TG
Transmission gate openswhen selected to chargeor discharge capacitor.This charge stores the bit.
INTRO. TO COMP. ENG.
CHAPTER X-
MEMORY UNITS
SPECIFICATION
MEMORY SYSTEMS
- MEMORY SYSTEMS • STATIC RAM • DYNAMIC RAM
-DRAM CELLS
-^
Having developed bit cells, either SRAM or DRAM bit cells, they can nowbe pieced together forming a memory unit.
-^
What do we want to specify in the design of a memory unit? •^
The number of bits.
•^
This gives the total number of bits that the memory unit can store.
•^
The grouping of bits into words.
•^
Accessing 1 bit at a time might be inconvenient, so, grouping bitsinto words is often done.
-^
Common examples of word bit sizes are 4, 8, 16, 32, and 64.
•^
The number of words in the memory unit (addressable words).
•^
This is a function of the word size and total number of bits.
INTRO. TO COMP. ENG.
CHAPTER X-
MEMORY UNITS
DESCRIPTION
MEMORY SYSTEMS
- STATIC RAM • DYNAMIC RAM • MEMORY UNITS
-SPECIFICATION
-^
In describing the capacity of a memory unit, the following is used •^
addresses x word size
•^
Example:
1Mx
-^
If a memory unit is described as 1Mx8, then it has •^
addresses,
•^
bits per word at each address location,
-^
data lines for the
^8
bit words,
•^
address lines to specify the
addresses,
•^
and
bits in the entire memory unit.
1M
(^20)
1M
(^20)
)^
)^
INTRO. TO COMP. ENG.
CHAPTER X-
MEMORY UNITS^ BLOCK DIAGRAM (1)
MEMORY SYSTEMS
- MEMORY UNITS
-SPECIFICATION-DESCRIPTION-DESCRIPTION EXAMPLES
-^
Below is a general block diagram for a memory unit. •^
The k address lines access a word in the memory for input or output.
-^
To simplify drawing, we now form buses of
n
(or
k
) lines.
Memory unit
k^
words
n
bits per word
ReadWrite
k
address lines
n
data output lines n
data input lines
k
R W
INTRO. TO COMP. ENG.
CHAPTER X-
MEMORY UNITS^ BLOCK DIAGRAM (2)
MEMORY SYSTEMS
- MEMORY UNITS
-DESCRIPTION-DESCRIPTION EXAMPLES-BLOCK DIAGRAM
-^
To conserve pins, the following layout is more common in practice. •^
The data lines are both input and output lines (not simultaneously).
•^
This is done by using tristate buffers to form a tristate bus (orsometimes referred to as a three-state bus).
Memory unit
k^
words
n
bits per word
Read/Write
Enable
k
address lines
n
data lines (input and output)
k
R/W CS
INTRO. TO COMP. ENG.
CHAPTER X-
MEMORY UNITS READ/WRITE OF 1-BIT
MEMORY SYSTEMS
- MEMORY UNITS
-DESCRIPTION EXAMPLES-BLOCK DIAGRAM-INTERNAL STRUCTURE
-^
In read mode: •^
Row decoder
activates
”^
all bit cells in that row.
•^
Each bit cell in the row outputs their stored bit.
•^
Column decoder takes the bit from only one column of the activated row.
-^
In write mode: •^
Row decoder
activates
”^
all bit cells in that row.
•^
Each bit cell in the row effectively outputs their stored bit.
•^
Column decoder selects the appropriate column and writes the input bit.
•^
SRAM: This writing is done by
overpowering
”^
what is being read by
the bit cell with a stronger voltage/current.
-^
DRAM: This writing is done by recharging the capacitor for writing a 1
or discharging the capacitor for writing a
^0
INTRO. TO COMP. ENG.
CHAPTER X-
MEMORY UNITS
CONTROL LINES (1)
MEMORY SYSTEMS
- MEMORY UNITS
-BLOCK DIAGRAM-INTERNAL STRUCTURE-READ/WRITE OF BIT
-^
Now include
k
address lines, 1-bit data line, Enable, and ~Read/Write.
Row Decoder
InputColumn Decoder
Bit Cell Matrix
Output
TG
TG
Enable R/W
D
Address lines
Address lines
p
k-p
INTRO. TO COMP. ENG.
CHAPTER X-
MEMORY UNITS
# BITS FOR ROWS/COLUMNS
MEMORY SYSTEMS
- MEMORY UNITS
-INTERNAL STRUCTURE-READ/WRITE OF BIT-CONTROL LINES
-^
In general, given a certain size memory chip, such as a 1Mx1 memory chip,we would not know how the internal matrix is configured. •^
For a
1Mx1 memory chip
, we know it has
20 address lines
(for our
purposes in any case, there are exceptions in the real world). Anycombination of address lines for the row and column decoder could beused to form the matrix.
•^
Example:
10 row
address lines and
10 column
address lines for a
1024x1024 matrix
of bit cells.
•^
Example:
12 row
address lines and
8 column
address lines for a
4096x256 matrix
of bit cells.
•^
Example:
5 row
address lines and
15 column
address lines for a
32x
matrix of bit cells.
INTRO. TO COMP. ENG.
CHAPTER X-
MEMORY UNITS
MULTIPLE BITS (WORDS)
MEMORY SYSTEMS
- MEMORY UNITS
-READ/WRITE OF BIT-CONTROL LINES-# BITS FOR ROWS/COLS.
-^
As noted, the described internal bit cell matrix structure accesses only 1 bitat a time.
-^
Multiple bits to form an
n
-bit word could be accessed in a few different
methods. •^
One method is to have the
column decoder
select a set of
n
columns
simultaneously
to form the word.
•^
This only works if the entire word is stored in one row. Hence, thereshould be a multiple of
n
columns in the bit cell matrix.
•^
For instance, the given bit cell matrix with 8 columns could easilyhave words of size 1, 2, 4, or 8.
•^
Another method, though arguably very similar, is to
duplicate
the entire
bit cell matrix
n
times
to form the
n
-bit word.