Notes on Single Cycle Datapath - Introduction to Computer Engineering | ECE 2030, Study notes of Electrical and Electronics Engineering

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Barrel Shifter/Single Cycle

Datapath

ECE

Shifter Implementation with Multiplexers

A 3

A 2

A 1

A 0

B 3

B 2

B 1

B 0

4:1 MUX

S

S S

d

4:1 MUX

S

S S

d

4:1 MUX

S

S S

d

4:1 MUX

S

S S

d

S=0 no shift S=1 shift d=1 shift right d=0 shift left

‘ 0 ’ ‘ 0 ’

1 shifter (logical shift)

A 0

A 1 A 2

A 3

A 2

A 1

A 3

A 2

A 1

A 0

B 3

B 2

B 1

B 0

4:1 MUX

S

S S

d

4:1 MUX

S

S S

d

4:1 MUX

S

S S

d

S=0 no shift S=1 shift d=1 shift right d=0 shift left

1 shifter (rotational shift)

A 0

A 1 A 2

A 3

A 2

A 1

Shifter Implementation with Multiplexers

4:1 MUX

S

S S

d

A 3 A 0

Shifter Implementation with Multiplexers

A 3

A 2

A 1

A 0

B 3

B 2

B 1

B 0

4:1 MUX

S

S S

d

4:1 MUX

S

S S

d

4:1 MUX

S

S S

d

4:1 MUX

S

S S

d

S=0 no shift S=1 shift d=1 shift right d=0 shift left

‘ 0 ’ ‘ 0 ’

2 shifter (logical shift)

A 0 A 1

A 3

A 2

‘ 0 ’ ‘ 0 ’

To find a more efficient implementation consider a unsigned binary number.

H

k

H

k-

… H

2

H

1

H

0

2 4 2 1

k

2

k-

…

If H i

is 1 then add 2

i

to the total to get a decimal number!

Barrel Shifter!

1-Shifter S

d

2-Shifter S

d

n

n

n

2

k

-Shifter S

d

n

Direction

H 0 H 1 H k

4-Shifter S

d

n

(H

k

H

k-

… H

2

H

1

H

0

= Shift Amount)

Shifter Unit in our datapath

X

Y Y Contains the

shift amount!!!

Y>0 shift right

Y<0 shift left

SU

su en

2

st

st

1

st 0

0 0

0 1

1 0

1 1

Logical

Arithmetic

Rotational

SINGLE CYCLE DATAPATH

General Purpose Register Architecture

Immediate Register

32- bit Immediate Register

Immediate Value

Constant value that comes directly

from instruction to datapath

im en

clk

32

X Y^ Z

rwe

au en

lu en

a/s

su en

lf

st

AU (^) LU SU

addr

register

file

32 x 32

X out

Y out

write Z

clk

32 - bit Immediate Register

Immediate Value

im en

clk

32

im en = low "Im Register" output is in the high impedance state

im en = high "Y out " is in the high impedance state

I 15

I 14

I 13

I 12

I 11

I 10

I 9

I 8

I 7

I 6

I 5

I 4

I 3

I 2

I 1

I 0

I

15

I 15

I 15

I 15

I 15

I 15

I 15

I 15

I 15

I 15

I 15

I 15

I 15

I 15

I 15

I 15

I 15

I 14

I 13

I 12

I 11

I 10

I 9

I 8

I 7

I 6

I 5

I 4

I 3

I 2

I 1

I 0

Sign extension

32

16

Assume negative number uses 2's complement!!!

X Y^ Z

rwe

au en

lu en

a/s

su en

lf

st

AU (^) LU SU

addr

register

file

32 x 32

X out

Y out

write Z

clk

Sign extension

clk

im en

Immediate Value

Single Cycle Datapath with Sign Extension

How do I control the datapath to do what I want??

$R0 = $R1 + $R

X Y Z rwe imm en im va au en a/s lu en lf su en st

1 2 0 1 0 X 1 0 0 xxxx 0 x

Register Transfer Level (RTL)

X Y^ Z

rwe

au en

lu en

a/s

su en

lf

st

4 2

AU LU SU

5 5

5

addr

register

file

32 x 32

X out

Y out

write Z

32

32

32

32

clk

Sign extension

clk

im en

Immediate Value

32

16

R3=R1 XOR R

How do I control the datapath to do what I want??

X Y Z rwe imm en im va au en a/s lu en lf su en st

1 5 3 1 0 X 0 x 1 0110 0 x

X Y^ Z

rwe

au en

lu en

a/s

su en

lf

st

4 2

AU (^) LU SU

5 5

5

addr

register

file

32 x 32

X out

Y out

write Z

32

32

32

32

clk

Sign extension

clk

im en

Immediate Value

32

16