Memory Technology, Lecture Slide - Computer Science, Slides of Introduction to Computers

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Memory Technology

Oct. 20, 1998

Topics

• Memory Hierarchy Basics
• Static RAM
• Dynamic RAM
• Magnetic Disks
• Access Time Gap

class17.ppt

Computer System

diskDisk Disk disk

Memory-I/O busMemory-I/O bus

ProcessorProcessor

CacheCache

MemoryMemory

I/O

controller

I/O

controller

I/O

controller

I/O

controller

I/O

controller

I/O

controller

DisplayDisplay NetworkNetwork

Reg

Scaling to 0.1μm

• Semiconductor Industry Association, 1992 Technology Workshop
  • Projected future technology based on past trends

Year 1992 1995 1998 2001 2004 2007

Feature size 0.5 0.35 0.25 0.18 0.12 0.

• Industry is slightly ahead of projection

DRAM cap 16M 64M 256M 1G 4G 16G

• Doubles every 1.5 years
• Prediction on track

Chip cm^2 2.5 4.0 6.0 8.0 10.0 12.

• Way off! Chips staying small

Static RAM (SRAM)

Fast

• ~6 ns [1998]

Persistent

• as long as power is supplied
• no refresh required

Expensive

• ~$100/MByte [1995]
• 6 transistors/bit

Stable

• High immunity to noise and environmental disturbances

Technology for caches

SRAM Cell Principle

Inverter Amplifies

• Negative gain
• Slope < –1 in middle
• Saturates at ends

Inverter Pair Amplifies

• Positive gain
• Slope > 1 in middle
• Saturates at ends V V

Vin

0 0.2 0.4 0.6 0.8 1

0

1

Vin V

V

Slope < –

Slope > 1

Bistable Element

Stability

• Require Vin = V
• Stable at endpoints
  • recover from pertubation
• Metastable in middle
  • Fall out when perturbed

Ball on Ramp Analogy

Vin V

V

Vin V

Vin

0 0.2 0.4 0.6 0.8 1

0

(^1) Stable

Metastable

Stable (^0) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Dynamic RAM (DRAM)

Slower than SRAM

• access time ~70 ns [1995]

Nonpersistant

• every row must be accessed every ~1 ms (refreshed)

Cheaper than SRAM

• ~$1.50 / MByte [1998]
• 1 transistor/bit

Fragile

• electrical noise, light, radiation

Workhorse memory technology

Anatomy of a DRAM Cell

Word Line

Bit Line

Storage Node

Access Transistor (^) C node

CBL

Writing

Word Line

Bit Line

Reading

Word Line

Bit Line

∆V ~ Cnode / CBL

V Storage Node

Example 2-Level Decode DRAM (64Kx1)

Row address latch

Row address latch

Column address latch

Column address latch

Row decoder

Row decoder 256x cell array

256x cell array

column latch and decoder

column latch and decoder

A7-A

\

\

R/W’

Dout Din

CAS

RAS

row

col

256 Rows

256 Columns column sense/write amps

column sense/write amps

Provide 16-bit address in two 8-bit chunks

DRAM Operation

Row Address (~50ns)

• Set Row address on address lines & strobe RAS
• Entire row read & stored in column latches
• Contents of row of memory cells destroyed

Column Address (~10ns)

• Set Column address on address lines & strobe CAS
• Access selected bit
  • READ: transfer from selected column latch to Dout
  • WRITE: Set selected column latch to Din

Rewrite (~30ns)

• Write back entire row

Enhanced Performance DRAMs

Row addresslatch

Row addresslatch

Column address latch

Column address latch

Row decoder

Row decoder (^) 256x cell array cell array256x

sense/write amps

sense/write amps

column latch and decoder

column latch and decoder

A7-A

(^8) \

(^8) \

R/W’

CAS

RAS

row

col

Entire row buffered here

row access time col access time cycle time page mode cycle time 50ns 10ns 90ns 25ns

Conventional Access

• Row + Col
• RAS CAS RAS CAS ...

Page Mode

• Row + Series of columns
• RAS CAS CAS CAS ...
• Gives successive bits

Other Acronyms

• EDORAM

• “Extended data output”
• SDRAM
• “Synchronous DRAM” Typical Performance

Performance Enhanced for Video / Graphics Operations

• Frame buffer to hold graphics image

Writing

• Random access of bits
• Also supports rectangle fill operations
  • Set all bits in region to 0 or 1

Reading

• Load entire row into shift register
• Shift out at video rates

Performance Example

• 1200 X 1800 pixels / frame
• 24 bits / pixel
• 60 frames / second
• 2.8 GBits / second

256x cell array

256x cell array

Shift RegisterShift Register

column sense/write amps

column sense/write amps

Video Stream Output

Video RAM

DRAM Storage Capacitor

d

Dielectric Material Dielectric Constant ε

Plate Area A

C = ε A/d

Planar Capacitor

• Up to 1Mb
• C decreases linearly with feature size

Trench Capacitor

• 4–256 Mb
• Lining of hole in substrate

Stacked Cell

• > 1Gb
• On top of substrate
• Use high ε dielectric

Trench Capacitor

Process

• Etch deep hole in substrate
  • Becomes reference plate
• Grow oxide on walls
  • Dielectric
• Fill with polysilicon plug
  • Tied to storage node Storage Plate Reference Plate

SiO 2 Dielectric