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The Memory Hierarchy

15-­‐213: Introduc0on to Computer Systems

9 th^ Lecture, Sep. 21, 2010

Instructors:

Randy Bryant and Dave O’Hallaron

Today

 Storage technologies and trends

 Locality of reference

 Caching in the memory hierarchy

SRAM vs DRAM Summary

Trans. Access Needs Needs

per bit time refresh? EDC? Cost Applications

SRAM 4 or 6 1X No Maybe 100x Cache memories

DRAM 1 10X Yes Yes 1X Main memories,

frame buffers

ConvenAonal DRAM OrganizaAon

 d x w DRAM:

 dw total bits organized as d supercells of size w bits

cols

rows

Internal row buffer

16 x 8 DRAM chip

addr

data

supercell (2,1)

2 bits /

8 bits /

Memory controller (to/from CPU)

Reading DRAM Supercell (2,1)

Cols

Rows

Internal row buffer

16 x 8 DRAM chip

CAS = 1

addr

data

2 /

8 /

Memory controller

supercell (2,1)

supercell (2,1)

To CPU

Memory Modules

: supercell (i,j)

64 MB

memory module consisting of eight 8Mx8 DRAMs

addr (row = i, col = j)

Memory controller

DRAM 7

DRAM 0

63 56 55 4847 40 39 3231 2423 1615 8 7 0

64-bit doubleword at main memory address A

bits 0-

bits 8-

bits 16-

bits 24-

bits 32-

bits 40-

bits 48-

bits 56-

64-bit doubleword

63 56 55 4847 40 39 3231 2423 1615 8 7 0

NonvolaAle Memories

 DRAM and SRAM are volaAle memories

 Lose informa0on if powered off.

 NonvolaAle memories retain value even if powered off

 Read-­‐only memory (ROM): programmed during produc0on

 Programmable ROM (PROM): can be programmed once

 Eraseable PROM (EPROM): can be bulk erased (UV, X-­‐Ray)

 Electrically eraseable PROM (EEPROM): electronic erase capability

 Flash memory: EEPROMs with par0al (sector) erase capability

 Wears out aaer about 100,000 erasings.

 Uses for NonvolaAle Memories

 Firmware programs stored in a ROM (BIOS, controllers for disks,

network cards, graphics accelerators, security subsystems,…)

 Solid state disks (replace rota0ng disks in thumb drives, smart

phones, mp3 players, tablets, laptops,…)

 Disk caches

TradiAonal Bus Structure ConnecAng

CPU and Memory

 A bus is a collecAon of parallel wires that carry address,

data, and control signals.

 Buses are typically shared by mulAple devices.

Main memory

I/O

bridge

Bus interface

ALU

Register file

CPU chip

System bus Memory bus

Memory Read TransacAon (2)

 Main memory reads A from the memory bus, retrieves

word x, and places it on the bus.

ALU

Register file

Bus interface

x^0

x A

Main memory

%eax

I/O bridge

Load operation: movl A, %eax

Memory Read TransacAon (3)

 CPU read word x from the bus and copies it into register

%eax.

x

ALU

Register file

Bus interface (^) x

Main memory 0

A

%eax

I/O bridge

Load operation: movl A, %eax

Memory Write TransacAon (2)

 CPU places data word y on the bus.

y

ALU

Register file

Bus interface

y

Main memory 0

A

%eax

I/O bridge

Store operation: movl %eax, A

Memory Write TransacAon (3)

 Main memory reads data word y from the bus and stores

it at address A.

y

ALU

register file

bus interface (^) y

main memory 0

A

%eax

I/O bridge

Store operation: movl %eax, A

Disk Geometry

 Disks consist of plaRers, each with two surfaces.

 Each surface consists of concentric rings called tracks.

 Each track consists of sectors separated by gaps.

Spindle

Surface

Tracks

Track k

Sectors

Gaps

Disk Geometry (Muliple-­‐PlaRer View)

 Aligned tracks form a cylinder.

Surface 0

Surface 1 Surface 2

Surface 3 Surface 4

Surface 5

Cylinder k

Spindle

Platter 0

Platter 1

Platter 2