ECE 2030
Section C
Midterm II
March 7th, 2008
Solutions
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Solutions to ECE 2030 Midterm II - Section C - March 7th, 2008 - Prof. Sudhakar Yalamanchi, Exams of Electrical and Electronics Engineering
The solutions to the midterm exam of ece 2030 - section c, held on march 7th, 2008. Various topics such as priority encoders, rom design, pla implementation, number systems conversion, and arithmetic operations. Students can use this document as a reference to check their understanding of these concepts.
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ECE 2030
Section C
Midterm II
March 7
th
Solutions
- Consider the following network of building block components. Fill in the table below to show the input to which an output is connected after each successive clock cycle. The input to the priority encoder is a shift register that performs a rotate right operation on each clock cycle and is initialized to the value shown after clock cycle 0.
Priority Encoder
4:1 Mux 1: DeMux
S1 S
S1 S0 S1^ S
A
B
C
D
W
X
Y
Z
I 0 I 1 I 2 I 3 S 1 S 0
0 1 X 0 0 1
0 X X 1 1 1
1 X X X 0 0
Clock^ Priority Encoder Specification Cycle
W X Y Z
1 0 0 0 D
2 A 0 0 0
3 0 0 0 D
4 A 0 0 0
5 0 0 0 D
- Implement the following expression in the PLA by providing all of the appropriate annotations.
F = BC + ACB = BC + A + C + B
0 or 1?: ___
0 or 1?: 0_
A B C
Note that further expression simplification is possible with a different answer.
- Convert the following numbers from one notation to the other. a. Between number systems
(10011.10001) 2 ___________13.88___________ (^16)
(124) 8 __________84____________ (^10)
(14.78125) 10 ___0x416C8000____IEEE Single Precision FP notation (Hexadecimal)
b. What is the smallest (in magnitude) number that can be represented in single precision IEE 754 floating point format? What happens if this number is multiplied by itself?
2-149 (denormalized).
If multiplied by itself it will result in underflow – the number will be too small to be represented with the single precision format.
- Arithmetic a. Perform the following signed operations. The numbers are represented in two’s complement form. Identify the operations for which overflow occurs assuming they are 6 bit two’s complement numbers.
___________ ________
b. Perform the addition of the following unsigned numbers and identify those operations for which overflow occurs assuming the number of bits available are the number of bits in the operands.
111011 010011
- 100001 + 110001
011100 0001000
Overflow? ____yes______ _____yes____
Overflow? No No
- Consider the following arrangement of two single bit D flip flops.
FF
D
FF
WE
WE
Q
- Using D Flip Flops (as shown below) and basic building blocks and gates, design a 3-bit shift register that includes the following functionality – shift right, shift left, rotate right, rotate left, and initialize to a new value. Create and use whatever control signals that you need. This is a design problem with multiple possible solutions. Provide the truth table showing the functionality of the control signals.
S2 S1 S0 Funtion 0 0 0 Keep Value 0 0 1 Shift Right 0 1 0 Shift Left 0 1 1 Rotate Right 1 0 0 Rotate Left 1 0 1 Load Value 1 1 0 Not Used 1 1 1 Not Used
Flip Flop