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ECE 2030 Assignment #3 by Yalamanchili: Digital Logic and Number Systems - Prof. Sudhakar , Assignments of Electrical and Electronics Engineering

Georgia Institute of Technology - Main CampusElectrical and Electronics Engineering
Prof. Sudhakar Yalamanchili

The third assignment for the ece 2030: digital logic and number systems course at the georgia institute of technology. The assignment includes various problems on truth tables, building logic circuits, binary and hexadecimal conversions, and 2's complement computations.

Typology: Assignments

Pre 2010

Uploaded on 08/04/2009

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Yalamanchili
GEORGIA INSTITUTE OF TECHNOLOGY
School of Electrical and Computer Engineering
ECE 2030: Sections C & D
Spring 2008
Assignment #3
Due Date: Monday, March 3rd in class. No late assignments will be accepted.
Problem 3.1
Fill the truth table for the circuit shown below. The truth table for the priority encoder is
shown below.
A B C S1 S0
I0 I
1 I2 I3 S1 S2
0 0 1 0 1 0
0 1 X 0 0 1
0 X X 1 1 1
1 X X X 0 0
pf3

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GEORGIA INSTITUTE OF TECHNOLOGY

School of Electrical and Computer Engineering

ECE 2030: Sections C & D

Spring 2008

Assignment

Due Date: Monday, March 3rd^ in class. No late assignments will be accepted.

Problem 3.

Fill the truth table for the circuit shown below. The truth table for the priority encoder is shown below.

A B C S 1 S 0

I 0 I 1 I 2 I 3 S 1 S 2

0 1 X 0 0 1

0 X X 1 1 1

1 X X X 0 0

Problem 3.

Build a single-bit Full adder using multiplexor and gates.

Problem 3.

Build a logic circuit that takes in a 4 bit input and computes the number of 1’s in the input. You may use basic gates and/or building blocks. Note that there are many different solutions. Use any combination of techniques that you wish.

Problem 3.

Perform the following conversions: (110.1101) 2 = ( ) (^16) (43.716) 10 = ( ) (^2) (ABCD.FF) 16 = ( ) (^10) (11.11) 16 = ( ) (^2)

Provide the hexadecimal representation of the IEEE 754 double precision floating point encodings of the following. (-1.0) 10 +infinity (-0.000001) 2

Problem 3.

Perform the following computations using 6-bit 2’s complement representation. Indicate if there is overflow. (a) 011110 – 011001 = (b) 011101 + 0011 = (c) 01011 – 0110 = (d) 1001 – 010010 =