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Material Type: Exam; Class: COMPU ARCHITECT PRIN; Subject: COMPUTER DESIGN/ARCHITECTURE; University: University of Florida; Term: Unknown 1989;
Typology: Exams
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Integer ALU 1 1 load/store 2 1 (memory unit) ADDD/SUBD 3 1 MULD/DIVD 7 1
Simulate the execution of a code segment in the provide tables. Both executions are on two- issue dynamic-scheduling pipeline microarchitectures with and without speculations. Note that both microarchitectures include a reorder buffer (infinite size) to enforce in-order commit with up to 2 commits per cycle, and both are equipped with 2 parallel CDBs for 2 concurrent writebacks. In both microarchitectures, store does not access memory until commit. Iter. Instruction Issue Execute Memory Wr-CDB Commit 1 LD^ F3,0(R1)^1 2 3 5 1 MULD^ F10,F3,F0^1 6 13 1 ADDD^ F12,F9,F10^2 14 17 1 SD^ 0(R1),F12^2 3 1 ADDIU R1,R1,#8^3 4 5 1 BNEZ^ R1,LOOP^3 6 2 LD^ F3,0(R1)^4 7 8 10 2 MULD^ F10,F3,F 2 ADDD^ F12,F9,F 2 SD^ 0(R1),F 2 ADDIU R1,R1,# 2 BNEZ^ R1,LOOP Part 1 - Simulating Execution without Speculation