MIMD Classification
Based on the memory organization and
interconnect strategy, the MIMD machines
are classified as:
Centralized Shared Memory
Architecture
Distributed Memory Architecture
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MIMD Classification-Advance Computer Architecture-Lecture Slides, Slides of Advanced Computer Architecture
This course focuses on quantitative principle of computer design, instruction set architectures, datapath and control, memory hierarchy design, main memory, cache, hard drives, multiprocessor architectures, storage and I/O systems, computer clusters. This lecture includes: Mimd, Classification, Shared, Memory, Architechture, Centralized, Strategy, Interconnect
Typology: Slides
2011/2012
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MIMD Classification
Based on the memory organization and interconnect strategy, the MIMD machines are classified as:
Centralized Shared Memory
Architecture
Distributed Memory Architecture
Centralized Shared-Memory
The Centralized Shared Memory design, shown here, illustrates the interconnection of main memory and I/O systems to the processor-cache subsystems
In small-level designs, with less than a dozens processor-cache, subsystems share the same physical centralized memory connected by a bus; while
In larger designs, i.e., the designs with a few …
Centralized Shared-Memory
… dozens processor- cache subsystems, the single bus is replaced with multiple buses or even a switch are used
However, the key architectural property of the Centralized Shared Memory design is the Uniform Memory Access – UMA;
i.e., the access time to all memory from all the processors is same
the single
Centralized Shared-Memory
Furthermore, the single main memory has a symmetric relationship to all the processors
These multiprocessors, therefore are referred to as the Symmetric (Shared Memory) Multi-Processors (SMP)
This style of architecture is also sometimes called the Uniform Memory Access (UMA) as it offers uniform access time to all the memory from all the processors
Decentralized Memory Architecture
Decentralized or Distributed Memory
interconnected by a small bus or a different interconnection technology
Furthermore, it is a cost effective way to scale the memory bandwidth if most of the accesses are to the local memory in the node
Thus, the distributed memory provides more memory bandwidth and lower memory latency
Parallel Architecture Issues
While studying parallel architecture we will be considering the following fundamental issues that characterize parallel machines:
- How large is a collection of processor? - How powerful are processing elements? - How do they cooperate and communicate? - How are data transmitted? - What type of interconnection? - What are HW and SW primitives for programmer? and - how does it translate into performance?
Issues of Parallel Machines
These issues can be classified as:
1) Naming
2) Synchronization
3) Latency and Bandwidth
Fundamental Issue #1: Naming
The segmented shared address space locations are named uniformly for all processes of the parallel program as: <process number, address> Choice of naming affects:
- code produced by a compiler as for message passing via load, the compiler just remembers address or keep track of processor number and local virtual address
Fundamental Issue #1: Naming
- replication of data, because in case of cache memory hierarchy the replication and consistency through load or via SW is affected by naming
- Global Physical and Virtual address space, as naming determines if the address space of each process can be configured to contain all shared data of the parallel program
Issue #3: Latency and Bandwidth
Bandwidth
- Need high bandwidth in parallel communication; however, bandwidth cannot be scaled, but stays close to the requirements
- Match limits in network, memory, and processor
- Overhead to communicate is a problem in many machines