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Digital Circuits: Modeling Synchronous Logic Elements - Latches, Flip-Flops, and Counters, Study notes of Microprocessors

San Diego State University (SDSU)Microprocessors

This document, from dr. Khurram waheed's compe 470 course at san diego state university, covers the fundamentals of synchronous logic elements, including latches, flip-flops, and counters. Topics include the differences between latches and flip-flops, their modeling variations, advantages and disadvantages, and inferring latches in vhdl. The document also discusses the d-type flip-flop, its variations, and the comparison between level and edge-triggered flip-flops. Additionally, it covers linear feedback shift registers (lfsrs), their advantages, feedback configuration, and structural design aspects.

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Dr. Khurram Waheed
1
CompE 470
Digital Circuits
Chapter 7: Modeling Synchronous Logic
Circuits
Dr. Khurram Waheed
San Diego State University
2
CompE 470 - SDSU
Synchronous Circuits
Two basic types of synchronous elements
(or cell primitives) preferred in VHDL are
The D-type flow-through latch
The D-type flip-flop
Main Topics covered are
Latches, flip-flops
Linear feedback shift registers (LFSR)
Counters, Clock Dividers
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pf13
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pf1b
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Partial preview of the text

Download Digital Circuits: Modeling Synchronous Logic Elements - Latches, Flip-Flops, and Counters and more Study notes Microprocessors in PDF only on Docsity!

CompE 470

Digital Circuits

Chapter 7: Modeling Synchronous Logic

Circuits

Dr. Khurram Waheed

San Diego State University

CompE 470 - SDSU

Synchronous Circuits

„ Two basic types of synchronous elements

(or cell primitives) preferred in VHDL are

The D-type flow-through latch

The D-type flip-flop

„ Main Topics covered are

Latches, flip-flops

Linear feedback shift registers (LFSR)

Counters, Clock Dividers

CompE 470 - SDSU

Modeling Latch Circuits

„ A latch is a level-sensitive memory cell that is transparent to signals

from the D input to Q output when enabled, and holds the value of

last D on Q when disabled

t

t

t

t

Time

Clk

D

Q

(c) Timing diagram

D

Q

Clk Q

Clk D

x

Q ( t + 1 )

Q ( ) t

(a) Truth table (b) Graphical symbol

CompE 470 - SDSU

Modeling Latch Circuits (2)

„ Latch Modeling variations

Active high or low enable

Active high or low preset/clear

„ Advantages of Latches

Latches if configured properly allow for cycle

stealing

„ i.e., circuit can be made to execute faster than the

clock using phased versions of clock

CompE 470 - SDSU

Inferring Latches

„ A latch is synthesized from a HDL model when a

signal needs to hold its value over time

„ Some common latch inferring techniques

A case statement where all the branches are not

explicitly defined infers a latch (i.e., others clause not

specified)

„ Case statement should not be used to infer latches, rather it

should be enclosed either in an if or wait statements

Also inferred if a path through code exists such that a

particular signal is not updated (assigned) a new

value

CompE 470 - SDSU

Ex 7.1: Simple/Multiple latches

inferred using if statement

CompE 470 - SDSU

Ex 7.2: Modeling Latches with preset &

clear

CompE 470 - SDSU

Ex 7.3: Multiple gated enable latch

CompE 470 - SDSU

Ex 7.6: Inference from nested case

CompE 470 - SDSU

The D-type Flip-flop

„ The D-type FF is an edge triggered memory device (or

cell primitive) that transfers a signal’s value on its D-

input, to its Q output, when an active edge transition

occurs on the clock input

„ Variations

All variations possible in a latch, i.e., enable, clear/preset

Asynchronous or asynchronous clear/preset

Rising or falling edge triggered

CompE 470 - SDSU

D

Clock

Q

m

Q Q

s

D Q

Q

(a) Circuit

(b) Timing diagram

(c) Graphical symbol

D Q

Q

Master Slave

D

Clock

Q

Q

D Q

Q

Q

m

Q

s

Clk Clk

ƒObservations:

ƒThe flip-flop changes state at negative edge of

clock

ƒ> Symbol to indicate the change in state

corresponds to an edge, o to indicate negative edge

ƒHow can we make it to work on positive edge?

Master-Slave D Flip-flop

CompE 470 - SDSU

A positive-edge-triggered D flip-flop

(a) Circuit

D
Q
Q

(b) Graphical symbol

Clock

D

Clock

P
P
P
P
Q
Q

Edge-triggered D flip-flop

Advantage: Fewer NAND gates, so

smaller transistor level circuit

CompE 470 - SDSU

Flip-flop Inference (2)

„ Older methods to determine edges for bit type

variables

Clock’event and Clock =1 (positive edge) & vice versa

not Clock’stable and Clock=0 (negative edge ) Flip-

flop Inference

Disadvantage :

„ The edge is not uniquely identified using the above

technioque for multi-valued variables such as

std_logic, where a valid positive edge detection

may require

(Clock’event and Clock’last_value=0 and Clock = 1)

CompE 470 - SDSU

Comparison: wait & if statements

„ The wait statement delays the execution of the

whole process until its expression becomes true

This means that all signal assignments in the process

will infer one or more flip-flops

Note: there can be only one wait statement in the process and it should

be the first statement

„ The if statement does not stop the execution of

the whole process and therefore allows for

modeling of purely combinatorial logic co-

existing within the same process.

„ So, if Statement is preferred over the wait

statement

CompE 470 - SDSU

Ex 7.7: +ve & -ve clocked FFs

Preferred techniques

CompE 470 - SDSU

Ex 7.8: Various FF Inferences

CompE 470 - SDSU

Ex 7.9: Combinatorial Logic

between two FFs

CompE 470 - SDSU

A simple shift register

t

t

t

t

t

t

t

t

Q

Q

Q

Q

=Out

In

(b) A sample sequence

(a) Circuit

D

Q

Q

Clock

D

Q

Q

D

Q

Q

D

Q

Q

In Out

Q

Q

Q

Q

Shift Registers

CompE 470 - SDSU

A simple shift register

Q

Q

Q

Q

Clock

Parallel input

Parallel output

Shift/Load

Serial

input

D

Q

Q

D

Q

Q

D

Q

Q

D

Q

Q

7.8.2 Parallel Access Shift Register

CompE 470 - SDSU

Code for an n -bit left-to-right shift register

LIBRARY ieee ;

USE ieee.std_logic_1164.all ;

ENTITY shiftn IS

GENERIC ( N : INTEGER := 8 ) ;

PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;

Clock : IN STD_LOGIC ;

L, w : IN STD_LOGIC ;

Q : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;

END shiftn ;

ARCHITECTURE Behavior OF shiftn IS

BEGIN

PROCESS

BEGIN

WAIT UNTIL Clock'EVENT AND Clock = '1' ;

IF L = '1' THEN

Q <= R ;

ELSE

Genbits: FOR i IN 0 TO N-2 LOOP

Q(i) <= Q(i+1) ;

END LOOP ;

Q(N-1) <= w ;

END IF ;

END PROCESS ;

END Behavior ;

Example 7a: Generic Shift Register

CompE 470 - SDSU

Structural Design Aspects - LFSR

„ XOR or XNOR Feedback Gates

The feedback path may consist of all XOR or XNOR

gates. They are interchangeable

Given a particular tap settings, an LFSR will

sequence through the same number of values in a

loop before the loop repeats itself. The only

difference is that the sequences will be different

CompE 470 - SDSU

Structural Design Aspects – LFSR (2)

„ One-to Many or Many-to-One structure

Both type of structures can be implemented

It is possible to get two different implementation with same

logic cost

A one-to-many structure will always have a shorter worse

case clock-to-clock path delay as it only passes through a

single two input XOR (XNOR) gate, instead of a tree of

gates used for many-to-one case.

CompE 470 - SDSU

Structural Design Aspects – LFSR (3)

„ What taps to use?

The choice of which taps to use

determines how many values are

included in a sequence of pseudo-

random numbers before the sequence

is repeated

Maximal Length Sequence: A

sequence which will go through all

possible combinations of bits except for

the all zero combination

More than one tap combination may

generate a maximal length sequence,

e.g.,

„ 10 bits Î[2,9] or [6,9]

„ or twenty 4-tap combinations

„ or 28 six-tap combinations

„ The sequence in each LFSR generated

will be different

CompE 470 - SDSU

Structural Design Aspects – LFSR (4)

„ Avoiding becoming stuck in prohibited state

Using XOR gates, an LFSR will not sequence if all the

register bits contain zeros. It will in fact cycle zeros

indefinitely

Correspondingly, an all XNOR gates LFSR will be

stuck if all bits are 1

This must be avoided by

„ Using a reset to either preset or clear the individual register

FFs to a known good value. This is called hard-wiring

„ Provide a means of loading an initial seed value into the

register; either parallel or serial

„ Model extra circuitry that allows all 2

n

values to be included in

the sequence

CompE 470 - SDSU

Structural Design Aspects – LFSR (7)

„ Principle behind 2

n

Looping

Notice that the taps for maximal length sequences always

include taps from the ends (i.e., a group from MS Bits and a

group from LS Bits)

The MSB tap, when XORed (or XNORed) inverts the smaller

looping sequence from the taps at LS end.

Since the all zeros (or all ones) combinations never occurs in an

LFSR built by XOR gates (or XNOR gates), therefore

„ When all outputs except the MSB is at 0 Î MSB =1, this condition

is detected and MSB is forced to zero Æ a 0 feedback and all zeros

are moved in registers

„ This is done by XORing the NOR of all bits (except MSB) with the

rest of XOR gates in the feedback

„ So when all bits in LFSR are zero, this inversion sets the feedback

back to logic 1 and the regular sequence continues

CompE 470 - SDSU

Ex 7.10: One-to-

many 8-bit LFSR

modified for 2

n

sequences

CompE 470 - SDSU

Generic n-bit LFSR models

„ In VHDL, a generic model for LFSR can be

developed using generics in entity

The size of the LFSR is instantiated upon definition

„ Another technique can be to define a generic

procedure

Disadvantage: However, the feedback signal needs

to be modeled as a signal (not as a variable) which

must be read Î therefore the output must be of type

buffer or inout (because signals cannot be defined in

a procedure)

CompE 470 - SDSU

Ex 7.11: Generic n-bit LFSR

„ Construction

A 2-D array TapsArrayType is defined (has 31

elements that are 32 bits wide)

A variable TapsArray holds the possible

values of feedback taps, using an aggregate

syntax for efficiency

A generic variable Width is defined to specify

the size of the LFSR