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Cork Institute of Technology
Bachelor of Engineering (Honours) in Electronic Engineering – Stage 1
(Bachelor of Engineering in Electronic Engineering – Stage 1)
(NFQ – Level 8)
Summer 2005
Electronics
(Time: 3 Hours)
Instructions Answer Q1 (40 Marks) and any other 3 Questions (20 Marks each). Maximum available marks is 100.
Examiners: Prof. C. Burkley Mr. J. Ryan Dr. W. P. O’Connor
- (a) Perform the following number conversions, showing all workings. (i) C4B7.A5 16 to decimal (ii) 6914.85 10 to binary (iii) 6149.38 10 to hexadecimal [6 marks]
(b) Assuming a 8-bit number system, use the 2’s complement method to perform the following arithmetic. Verify and comment on your answer, showing all workings. (^011000112)
------------- [4 marks]
(c) Obtain a minimised logical expressed for the K-map in Fig.1(c). Then draw the corresponding minimised logic circuit using NOR gates only. [4 marks]
(d) Write a technical note on shift-registers. Your answer should include both block diagrams and logic diagrams as well as operational explanations. [6 marks]
(e) Draw a circuit diagram for a filtered bridge rectifier and explain the operation of each section using waveform diagrams. [6 marks]
(f) A Zener diode and one resistor are joined in series to provide a 16 V stabilised output from a 20 V supply. If the load resistor is 200 Ω and the current through the Zener is 8 mA, determine the value of the series resistor and the power dissipated in it. If the load is increased to 250 Ω , the output voltage rises to 16.2 V. Determine the current which then flows through the Zener diode. [4 marks]
(g) For the circuits shown in Fig. 1(g), sketch the expected output waveform, if the input in each case is 30 V p-p sinusoidal waveform. [4 marks]
(h) Design a practical common-emitter (C-E) amplifier using a voltage divider circuit, in which Vcc = 12V, VQ = 6V and I (^) Q = 1mA. The circuit should operate satisfactorily
using Si transistors whose values of hFE = β range from 50 to 200.
(outline/justify any assumptions that you make). [6 marks]
- (a) Explain how potential-divider biasing achieves stabilisation of the operating point (Q-point) in a common-emitter configuration. [4 marks]
(b) For the common-emitter amplifier shown in Fig.2, indicate your understanding of each component within the circuit from both an a.c and d.c point of view. [4 marks]
(c) With reference to Fig. 2
(i) Calculate the Q-point (V (^) CE and I (^) C ) (ii) Draw the a.c. equivalent circuit (iii) Calculate the a.c. voltage gain (iv) Determine the magnitude of the output a.c. voltage. [12 marks]
- (a) Compare the FET with the BJT in terms of (i) input impedance, input current and voltage. (ii) Output impedance, output current and voltage. [6 marks]
(b) For the JFET circuit shown in Fig.3, IDSS = 12mA, V (^) GS(OFF) = - 4V and gm = 2.9 mS, calculate (i) The quiescent point of the circuit (i.e. VGS and I (^) D ) (ii) The voltage gain of the amplifier (iii) Draw the a.c. equivalent circuit (iv) The output voltage (V (^) O), given an input signal (VS) of magnitude 0.4V to the circuit. (Assume capacitor has negligible effect). [14 marks]
A B C D
B A
C
D
Fig.1(c)
F ig. Q 1(g)(i)
in p u t 1 k o u p u t
F ig. Q 1(g)(ii)
in p u t 1 k o u p u t
F ig. Q 1(g)(iv)
in p u t o u p u t 1 0 V
F ig. Q 1 (g )(iii)
in p u t o u p u t
1 k
1 0 V o
o
o
o
o
o
o
o
o
o
o
o
o
1 k
o
o
o
+Vcc=12V
600
10K
1mV (^) 2.2K
1K
3.6K
10K
h = 100 fe
Fig. Q
--
N-Channel Junction
Vdd=18V
V 0.4V
Vout
R
s
s
R R
R R
R
d
L
s
2.7M
1.2M
220K
220K
4.7K
2.7K
Fig.
