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Module 1: "Multi-core: The Ultimate Dose of Moore's Law"
Lecture 1: "Evolution of Processor Architecture"
The Lecture Contains:
Multi-core: The Ultimate Dose of Moore’s Law
A gentle introduction to the multi-core landscape as a tale of four decades of glory and success
Mind-boggling Trends in Chip Industry
Agenda
Unpipelined Microprocessors
Pipelining
Pipelining Hazards
Control Dependence
Data Dependence
Structural Hazard
Out-of-order Execution
Multiple Issue
Out-of-order Multiple Issue
Module 1: "Multi-core: The Ultimate Dose of Moore's Law"
Lecture 1: "Evolution of Processor Architecture"
Mind-boggling Trends in Chip Industry:
Long history since 1971 Introduction of Intel 4004 http://www.intel4004.com/ Today we talk about more than one billion transistors on a chip Intel Montecito (in market since July’06) has 1.7B transistors Die size has increased steadily (what is a die?) Intel Prescott: 112mm2, Intel Pentium 4EE: 237 mm2, Intel Montecito: 596 mm Minimum feature size has shrunk from 10 micron in 1971 to 0.045 micron today
Agenda:
Unpipelined microprocessors Pipelining: simplest form of ILP Out-of-order execution: more ILP Multiple issue: drink more ILP Scaling issues and Moore’s Law Why multi-core TLP and de-centralized design Tiled CMP and shared cache Implications on software Research directions
Unpipelined Microprocessors:
Typically an instruction enjoys five phases in its life Instruction fetch from memory Instruction decode and operand register read Execute Data memory access Register write Unpipelined execution would take a long single cycle or multiple short cycles Only one instruction inside processor at any point in time
Module 1: "Multi-core: The Ultimate Dose of Moore's Law"
Lecture 1: "Evolution of Processor Architecture"
Data Dependence:
Take three bubbles?
Back-to-back dependence is too frequent
Solution: hardware bypass paths
Allow the ALU to bypass the produced value in time: not always possible
Need a live bypass! (requires some negative time travel: not yet feasible in real world)
No option but to take one bubble
Bigger problems: load latency is often high; you may not find the data in cache
Structural Hazard:
Usual solution is to put more resources
Module 1: "Multi-core: The Ultimate Dose of Moore's Law"
Lecture 1: "Evolution of Processor Architecture"
Out-of-order Execution:
