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Lecture
° Chapter 5
° Finish up section 5.
° Chapter 6
° Section 6.1 - pipelining
- Start with general idea
- Look at issues and problems
- Then talk about implementation next time
Single vs. Multi-cycle Implementation
° Single cycle design is simple
° But it’s inefficient
° Why?
° All instructions have same clock cycle length - they all take the same amount of time regardless of what they actually do
° Clock cycle determined by longest path
- Load: uses IM, RF, ALU, DM, RF in sequence
° But others may be shorter
Single vs. Multi-cycle Implementation
° For this simple version, the multi-cycle implementation could be as much as 1.27 times faster
° Suppose we had floating point operations
- Floating point has very high latency
- E.g., floating-point multiply may be 16 ns vs integer add may be 2 ns
- So, clock cycle constrained by 16 ns of FP
- Performance penalty is too big to tolerate
Multi-cycle Implementation
° Single memory unit (I and D), single ALU
° Several temporary registers (IR, MDR, A, B, ALUOut)
° Temporaries hold output value of element so the output value can be used on subsequent cycle
° Values needed by subsequent instruction stored in programmer visible state (memory, RF)
Multi-cycle Steps - Instruction Fetch
° Instruction fetch IR = Memory[PC]; PC = PC + 4;
° Operation
- Send PC to memory as the address
- Read instruction from memory
- Write instruction into IR for use on next cycle
- Increment PC by 4
- Uses ALU in this first cycle
- Set control signals to send PC and constant 4 to ALU
Multi-cycle Steps - Instruction Decode
° Don’t yet know what instruction is
- Decode the instruction concurrently with RF read
- Optimistically read registers
- Optimistically compute branch target
- We’ll select the right answer on next cycle
° Decode and Register File Read
A = Reg[IR[25-21]]; B = Reg[IR[20-16]]; ALUOut = PC + (sign-extend(IR[15-0]) << 2);
Multi-cycle Steps - Execution
° Operation varies based on instruction decode
° Memory reference: ALUOut = A + sign-extend(IR[15-0]);
° Arithmetic-logical instruction: ALUOut = A op B; ° Branch: if (A == B) PC = ALUOut; ° Jump: PC = PC[31-28] || IR[25-0] << 2)
Multi-cycle Steps - Memory / Completion
° Load/store accesses memory or arithmetic writes result to the register file
° Memory reference: MDR = Memory[ALUOut]; (load) or Memory[ALUOut] = B; (store)
° Arithmetic-logical instruction: Reg[IR[15-11]] = ALUOut;
Multi-cycle Control
° It’s more complex than single cycle -
- Instructions executed in a series of steps
- Control signals must be set on each cycle
- Must specify control on a cycle and the next step in the control sequence
° 2 basic implementation techniques
- Finite state machine (“hard wired control”)
- Microprogrammed control
FSM Control
° State machine: set of states & directions how to change change between states (transitions)
° State indicates control signals to set
° Transition indicates how to move from one state to another given inputs to that state
- Cycle indicates when to advance to next state
° The finite state control corresponds to five steps of instruction execution
FSM for Simple MIPS Implementation
Fetch (^) Decode
L/S instrs
R-format
Branch Jump
After decode, we know the instruction type and do the actions that are unique to that instruction type
Current state advanced on each clock cycle - the next state depends on current state and instruction class
Microprogrammed Control
° Similar to hard wired FSM control
° Except - there is an actual “program” that indicates how to set the control signals
° Program made up of “microinstructions”
° Microinstruction
- Indicates how to set control signal
- Next microinstruction
Pipelining
° How do we improve on the performance of the multi-cycle implementation?
° Key observation -
- we can be doing multiple things at once
° Pipelining -
- implementation technique to execute multiple instructions simultaneously
Pipelining is Natural!
° Laundry Example ° Ann, Brian, Cathy, Dave each have one load of clothes to wash, dry, and fold ° Washer takes 30 minutes
° Dryer takes 30 minutes
° “Folder” takes 30 minutes
° “Stasher” takes 30 minutes to put clothes into drawers
A B C D
Sequential Laundry
° We have four loads of laundry to do (A,B,C,D)
T^30
a s k O r d e r
B
C D
A
Time
6 PM 7 8 9 10 11 12 1 2 AM
Sequential Laundry
° First, we wash….
T^30
a s k O r d e r
B
C D
A
Time
6 PM 7 8 9 10 11 12 1 2 AM
Sequential Laundry
° Finally we put the clothes away…. ° It took us two hours to do one laundry…yikes! ° We have three loads remaining!
T^30
a s k O r d e r
B
C D
A
Time
6 PM 7 8 9 10 11 12 1 2 AM
Sequential Laundry
° Whew, it’s 10 pm already and two loads to go
T^30
a s k O r d e r
B
C D
A
Time
6 PM 7 8 9 10 11 12 1 2 AM
Sequential Laundry
° We finish at 2 AM (half asleep) ° Sequential laundry takes 8 hours for 4 loads ° If they pipelined it, how long would laundry take?
T^30
a s k O r d e r
B
C D
A
Time
6 PM 7 8 9 10 11 12 1 2 AM
Pipelined Laundry: Start work ASAP
° Let’s start to wash….
T a s k O r d e r
6 PM 7 8 9 10 11 12 1 2 AM
Time
B
C
D
A
Pipelined Laundry: Start work ASAP
° Fold first load, dry second load, start third load
T a s k O r d e r
6 PM 7 8 9 10 11 12 1 2 AM
Time
B
C
D
A
Pipelined Laundry: Start work ASAP
° Stash first load, fold second, dry third, wash fourth
T a s k O r d e r
6 PM 7 8 9 10 11 12 1 2 AM
Time
B
C
D
A
Pipelined Laundry: Start work ASAP
° Pipelined laundry takes 3.5 hours for 4 loads!
T a s k O r d e r
6 PM 7 8 9 10 11 12 1 2 AM
Time
B
C
D
A
Pipelining Lessons
° Pipelining doesn’t help latency of single task, it helps throughput of entire workload ° Multiple tasks operating simultaneously using different resources ° Potential speedup = Number pipe stages ° Pipeline rate limited by slowest pipeline stage ° Unbalanced lengths of pipe stages reduces speedup ° Time to “fill” pipeline and time to “drain” it reduces speedup ° Stall for Dependences
6 PM 7 8
Time
B
C
D
A
T a s k O r d e r
Pipelining for Instruction Execution - Example
° Let’s consider a single-cycle vs. pipelined implementation of simple MIPS
Inst. Reg ALU Mem. Reg Total Class Fetch Read Oper Acc. Write Time Load 2 ns 1 ns 2 ns 2 ns 1 ns 8 ns Store 2 ns 1 ns 2 ns 2 ns 7 ns R-type 2 ns 1 ns 2 ns 1 ns 6 ns Branch 2 ns 1 ns 2 ns 5 ns
° For single cycle implementation, the cycle time is stretched to accommodate the slowest instruction ° Cycle time: 8 ns for single cycle implementation
Single Cycle Implementation
Num. Instruction I1 lw $1,100($0) I2 lw $2, 200($0) I3 lw $3, 300($0)
I
I
I
Time for each instruction is 8 ns - slowest time (for load)
Time between 1st and 4th instruction is 3 * 8 ns = 24 ns
Total time = 24 ns
Fetch Reg ALU Memory Reg
Fetch Reg ALU Memory Reg
F
2 4 6 8 10 12 14 16
Pipelined Implementation
Num. Instruction I1 lw $1,100($0) I2 lw $2, 200($0) I3 lw $3, 300($0)
I
I
I
Each step takes 2 ns (even reg file access) - slowest step is 2 ns
Time between 1st and 4th instruction: 3 * 2 ns = 6 ns
Total time for the three instructions = 14 ns
Fetch Reg ALU Memory Reg
2 4 6 8 10 12 14 16
Fetch Reg ALU Memory Reg
Fetch Reg ALU Memory Reg
Conventional Pipelined Execution Representation
° Can help with answering questions like:
- how many cycles does it take to execute this code?
- what is the ALU doing during cycle 4?
- use this representation to help understand datapaths
IFetch Dcd Exec Mem WB IFetch Dcd Exec Mem WB IFetch Dcd Exec Mem WB IFetch Dcd Exec Mem WB IFetch Dcd Exec Mem WB Program Flow IFetch Dcd Exec Mem WB
Time
