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Shankar Balachandran*
Associate Professor, CSE Department
Indian Institute of Technology Madras
*Currently a Visiting Professor at IIT Bombay
Digital Circuits and
Systems
Spring 2015 Week 3 Module 14
Multiplexers
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Shankar Balachandran* Associate Professor, CSE Department Indian Institute of Technology Madras

*Currently a Visiting Professor at IIT Bombay

Digital Circuits and

Systems

Spring 2015 Week 3 Module 14

Multiplexers

Multiplexers

 Multiplexing means transmitting a large number of information

units over a smaller number of channels or lines.

 A digital multiplexer ( MUX ) selects binary information from one

of many input lines and directs it to a single output line.

 Data selector (2n:1 MUX).  Inputs: 2n^ data inputs, n select lines.  Output: 1 data output line.

s1 s0 Out 0 0 D 0 1 D 1 0 D 1 1 D

D0 D

0 1

D2 D

0

1

Out s1 s

s1 s (control)

D

D

D

D

Out

Internal Structure of a 4:1 MUX

 A 2n:1 MUX needs 2n, ( n +1)-input AND gates for selection and a 2 n-input OR gate to generate the final output.   AND/OR logic structure

Closeness to Decoders

En

D 2

D 3

D 1

D 0

Connect all the input lines of the multiplexer together (to make enable) and remove the OR gate to give you a decoder

Using 2:1 Muxes to Build a 4:1 Mux

0

w 0 w 1

0 1

w 2 w 3

0 1

f 0 1

s 1 s

Practical Application of Multiplexers

x 1 0 1

x 2 0 1

s

y 1

y 2

x 1 x 2

y 1 y 2

2x2 crossbar switch

s

MUX Based Logic

Advantages :  Easier to design combinational circuits.  Easier to debug circuits designed using multiplexers.  Disadvantages :  Multiplexers can become very large for a large number of inputs.

  Good for small circuits.

 Normally, any function with more than 4 variable is impractical for direct implementation (i.e., using a single large MUX).  Use tree of small MUXes or using a variable as MUX data input or Shannon’s Expansion Theorem for implementing large functions.

Multiplexer Tree

 A larger MUX can be implemented using a tree of smaller MUXes.  Example : Implement the function using smaller MUXes instead of one 8:1 MUX.

Fa ,b,c   (^)  1 , 2 , 4 , 7 