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Main points of this past exam are: Mux Required, Memory Systems, Offset Concatenate, Following Questions, Organization Approach, Answers in Decimal, Words Per Column, Decoder Required, Bit Memory System, Indicate Bit Width
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4 problems, 6 pages Exam Three 8 April 2009
Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate the pages of the exam. For maximum credit, show your work. Good Luck!
Your Name ( please print ) ________________________________________________
1 2 3 4 total
4 problems, 6 pages Exam Three 8 April 2009
Problem 1 (3 parts, 30 points) Memory Systems
Part A (12 points) Consider a DRAM chip organized as 4 million addresses of 64-bit words. Assume both the DRAM cell and the DRAM chip are square. The column number and offset concatenate to form the memory address. Using the organization approach discussed in class, answer the following questions about the chip. Express all answers in decimal (not powers of two).
number of columns
number of words per column column decoder required ( n to m )
total number of bits in address type of mux required ( n to m )
number of address lines in column offset
Part B (10 points) Consider a memory system with 16 million addresses of 32-bit words using a 2 million address by 8-bit word memory DRAM chip.
word address lines for memory system
chips needed in one bank
banks for memory system memory decoder required ( n to m )
DRAM chips required
Part C (8 points) Design a 32 million address by 8 bit memory system with four 16M x 4 memory chips. Label all busses and indicate bit width. Assume R/W is connected and not shown here. Use a bank decoder if necessary.
D D D D
ADDR
CS D D D D
ADDR
CS D D D D
ADDR
CS
ADDR
MSEL
D D D D
16M x 4
D D D D
ADDR
CS
16M x 4
16M x 4
16M x 4
D D D D
4 problems, 6 pages Exam Three 8 April 2009
Problem 3 (3 parts, 26 points) Microcode
Using the supplied datapath, write microcode fragments to accomplish the following procedures. Express all values, except memory addresses, in hexadecimal notation. Use ‘X’ when a value is don’t cared. For maximum credit, complete the description field. ⊕ means bitwise logical XOR. In each part, modify only registers 7 & 8. Part A (6 points) R 7 (^) = 15 ⋅ R 8 # X Y Z rwe im en
im va au en
-a /s
lu en
lf su en
st ld en
st en
r/ -w
msel description
1
2
3
Part B (12 points) Compute mem[3000] + 20 and store the result in mem[4000]. # X Y Z rwe im en
im va au en
-a /s
lu en
lf su en
st ld en
st en
r/ -w
msel description
1 2 3 4 5 6
Part C (8 points) Register 7 holds two packed 16 bit binary strings A and B as illustrated below. A B 31 16 15 0 Write a microcode sequence that unpacks A and B and computes R (^) 8 = A ⊕ B. # X Y Z rwe im en
im va au en
-a /s
lu en
lf su en
st ld en
st en
r/ -w
msel description
1
2
3
4
Assuming A and B are nonzero, what must be true about A and B for the result in R 8 to be zero?
4 problems, 6 pages Exam Three 8 April 2009
Problem 4 (2 parts, 20 points) Counters
Part A (10 points) Design a toggle cell using two transparent latches, two 2 to 1 muxes, and one inverter. Your toggle cell should have an active high toggle enable input TE , and an active low clear input CLR , clock inputs Φ 1 and Φ 2 , and an output Out. The CLR signal has precedence over TE. Label all signals. Also complete the behavior table for the toggle cell.
Out
TE (^) CLR CLK Out
Part B (10 points) Now combine these toggle cells to build a divide by seven counter. Your counter should have an external clear, external count enable, and three count outputs O 2 , O 1 , O 0. Use any basic gates (AND, OR, NAND, NOR, XOR & NOT) you require. Assume clock inputs to the toggle cells are already connected. Your design must support multi-digit systems.
CEOut
Clr
Toggle
CEOut
Clr
Toggle
CEOut
Clr
Toggle
